esp32p4/rsa/
int_clr.rs

1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `CLEAR_INTERRUPT` writer - Write 1 to clear the RSA interrupt."]
4pub type CLEAR_INTERRUPT_W<'a, REG> = crate::BitWriter<'a, REG>;
5#[cfg(feature = "impl-register-debug")]
6impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
7    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
8        write!(f, "(not readable)")
9    }
10}
11impl W {
12    #[doc = "Bit 0 - Write 1 to clear the RSA interrupt."]
13    #[inline(always)]
14    #[must_use]
15    pub fn clear_interrupt(&mut self) -> CLEAR_INTERRUPT_W<INT_CLR_SPEC> {
16        CLEAR_INTERRUPT_W::new(self, 0)
17    }
18}
19#[doc = "Clears RSA interrupt\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
20pub struct INT_CLR_SPEC;
21impl crate::RegisterSpec for INT_CLR_SPEC {
22    type Ux = u32;
23}
24#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
25impl crate::Writable for INT_CLR_SPEC {
26    type Safety = crate::Unsafe;
27    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
28    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
29}
30#[doc = "`reset()` method sets INT_CLR to value 0"]
31impl crate::Resettable for INT_CLR_SPEC {
32    const RESET_VALUE: u32 = 0;
33}
esp32p4/rsa/int_clr.rs

esp32p4/rsa/
int_clr.rs
