1#[repr(C)]
2#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5 l1_icache_ctrl: L1_ICACHE_CTRL,
6 l1_dcache_ctrl: L1_DCACHE_CTRL,
7 l1_bypass_cache_conf: L1_BYPASS_CACHE_CONF,
8 l1_cache_atomic_conf: L1_CACHE_ATOMIC_CONF,
9 l1_icache_cachesize_conf: L1_ICACHE_CACHESIZE_CONF,
10 l1_icache_blocksize_conf: L1_ICACHE_BLOCKSIZE_CONF,
11 l1_dcache_cachesize_conf: L1_DCACHE_CACHESIZE_CONF,
12 l1_dcache_blocksize_conf: L1_DCACHE_BLOCKSIZE_CONF,
13 l1_cache_wrap_around_ctrl: L1_CACHE_WRAP_AROUND_CTRL,
14 l1_cache_tag_mem_power_ctrl: L1_CACHE_TAG_MEM_POWER_CTRL,
15 l1_cache_data_mem_power_ctrl: L1_CACHE_DATA_MEM_POWER_CTRL,
16 l1_cache_freeze_ctrl: L1_CACHE_FREEZE_CTRL,
17 l1_cache_data_mem_acs_conf: L1_CACHE_DATA_MEM_ACS_CONF,
18 l1_cache_tag_mem_acs_conf: L1_CACHE_TAG_MEM_ACS_CONF,
19 l1_icache0_prelock_conf: L1_ICACHE0_PRELOCK_CONF,
20 l1_icache0_prelock_sct0_addr: L1_ICACHE0_PRELOCK_SCT0_ADDR,
21 l1_icache0_prelock_sct1_addr: L1_ICACHE0_PRELOCK_SCT1_ADDR,
22 l1_icache0_prelock_sct_size: L1_ICACHE0_PRELOCK_SCT_SIZE,
23 l1_icache1_prelock_conf: L1_ICACHE1_PRELOCK_CONF,
24 l1_icache1_prelock_sct0_addr: L1_ICACHE1_PRELOCK_SCT0_ADDR,
25 l1_icache1_prelock_sct1_addr: L1_ICACHE1_PRELOCK_SCT1_ADDR,
26 l1_icache1_prelock_sct_size: L1_ICACHE1_PRELOCK_SCT_SIZE,
27 l1_icache2_prelock_conf: L1_ICACHE2_PRELOCK_CONF,
28 l1_icache2_prelock_sct0_addr: L1_ICACHE2_PRELOCK_SCT0_ADDR,
29 l1_icache2_prelock_sct1_addr: L1_ICACHE2_PRELOCK_SCT1_ADDR,
30 l1_icache2_prelock_sct_size: L1_ICACHE2_PRELOCK_SCT_SIZE,
31 l1_icache3_prelock_conf: L1_ICACHE3_PRELOCK_CONF,
32 l1_icache3_prelock_sct0_addr: L1_ICACHE3_PRELOCK_SCT0_ADDR,
33 l1_icache3_prelock_sct1_addr: L1_ICACHE3_PRELOCK_SCT1_ADDR,
34 l1_icache3_prelock_sct_size: L1_ICACHE3_PRELOCK_SCT_SIZE,
35 l1_dcache_prelock_conf: L1_DCACHE_PRELOCK_CONF,
36 l1_dcache_prelock_sct0_addr: L1_DCACHE_PRELOCK_SCT0_ADDR,
37 l1_dcache_prelock_sct1_addr: L1_DCACHE_PRELOCK_SCT1_ADDR,
38 l1_dcache_prelock_sct_size: L1_DCACHE_PRELOCK_SCT_SIZE,
39 lock_ctrl: LOCK_CTRL,
40 lock_map: LOCK_MAP,
41 lock_addr: LOCK_ADDR,
42 lock_size: LOCK_SIZE,
43 sync_ctrl: SYNC_CTRL,
44 sync_map: SYNC_MAP,
45 sync_addr: SYNC_ADDR,
46 sync_size: SYNC_SIZE,
47 l1_icache0_preload_ctrl: L1_ICACHE0_PRELOAD_CTRL,
48 l1_icache0_preload_addr: L1_ICACHE0_PRELOAD_ADDR,
49 l1_icache0_preload_size: L1_ICACHE0_PRELOAD_SIZE,
50 l1_icache1_preload_ctrl: L1_ICACHE1_PRELOAD_CTRL,
51 l1_icache1_preload_addr: L1_ICACHE1_PRELOAD_ADDR,
52 l1_icache1_preload_size: L1_ICACHE1_PRELOAD_SIZE,
53 l1_icache2_preload_ctrl: L1_ICACHE2_PRELOAD_CTRL,
54 l1_icache2_preload_addr: L1_ICACHE2_PRELOAD_ADDR,
55 l1_icache2_preload_size: L1_ICACHE2_PRELOAD_SIZE,
56 l1_icache3_preload_ctrl: L1_ICACHE3_PRELOAD_CTRL,
57 l1_icache3_preload_addr: L1_ICACHE3_PRELOAD_ADDR,
58 l1_icache3_preload_size: L1_ICACHE3_PRELOAD_SIZE,
59 l1_dcache_preload_ctrl: L1_DCACHE_PRELOAD_CTRL,
60 l1_dcache_preload_addr: L1_DCACHE_PRELOAD_ADDR,
61 l1_dcache_preload_size: L1_DCACHE_PRELOAD_SIZE,
62 l1_icache0_autoload_ctrl: L1_ICACHE0_AUTOLOAD_CTRL,
63 l1_icache0_autoload_sct0_addr: L1_ICACHE0_AUTOLOAD_SCT0_ADDR,
64 l1_icache0_autoload_sct0_size: L1_ICACHE0_AUTOLOAD_SCT0_SIZE,
65 l1_icache0_autoload_sct1_addr: L1_ICACHE0_AUTOLOAD_SCT1_ADDR,
66 l1_icache0_autoload_sct1_size: L1_ICACHE0_AUTOLOAD_SCT1_SIZE,
67 l1_icache1_autoload_ctrl: L1_ICACHE1_AUTOLOAD_CTRL,
68 l1_icache1_autoload_sct0_addr: L1_ICACHE1_AUTOLOAD_SCT0_ADDR,
69 l1_icache1_autoload_sct0_size: L1_ICACHE1_AUTOLOAD_SCT0_SIZE,
70 l1_icache1_autoload_sct1_addr: L1_ICACHE1_AUTOLOAD_SCT1_ADDR,
71 l1_icache1_autoload_sct1_size: L1_ICACHE1_AUTOLOAD_SCT1_SIZE,
72 l1_icache2_autoload_ctrl: L1_ICACHE2_AUTOLOAD_CTRL,
73 l1_icache2_autoload_sct0_addr: L1_ICACHE2_AUTOLOAD_SCT0_ADDR,
74 l1_icache2_autoload_sct0_size: L1_ICACHE2_AUTOLOAD_SCT0_SIZE,
75 l1_icache2_autoload_sct1_addr: L1_ICACHE2_AUTOLOAD_SCT1_ADDR,
76 l1_icache2_autoload_sct1_size: L1_ICACHE2_AUTOLOAD_SCT1_SIZE,
77 l1_icache3_autoload_ctrl: L1_ICACHE3_AUTOLOAD_CTRL,
78 l1_icache3_autoload_sct0_addr: L1_ICACHE3_AUTOLOAD_SCT0_ADDR,
79 l1_icache3_autoload_sct0_size: L1_ICACHE3_AUTOLOAD_SCT0_SIZE,
80 l1_icache3_autoload_sct1_addr: L1_ICACHE3_AUTOLOAD_SCT1_ADDR,
81 l1_icache3_autoload_sct1_size: L1_ICACHE3_AUTOLOAD_SCT1_SIZE,
82 l1_dcache_autoload_ctrl: L1_DCACHE_AUTOLOAD_CTRL,
83 l1_dcache_autoload_sct0_addr: L1_DCACHE_AUTOLOAD_SCT0_ADDR,
84 l1_dcache_autoload_sct0_size: L1_DCACHE_AUTOLOAD_SCT0_SIZE,
85 l1_dcache_autoload_sct1_addr: L1_DCACHE_AUTOLOAD_SCT1_ADDR,
86 l1_dcache_autoload_sct1_size: L1_DCACHE_AUTOLOAD_SCT1_SIZE,
87 l1_dcache_autoload_sct2_addr: L1_DCACHE_AUTOLOAD_SCT2_ADDR,
88 l1_dcache_autoload_sct2_size: L1_DCACHE_AUTOLOAD_SCT2_SIZE,
89 l1_dcache_autoload_sct3_addr: L1_DCACHE_AUTOLOAD_SCT3_ADDR,
90 l1_dcache_autoload_sct3_size: L1_DCACHE_AUTOLOAD_SCT3_SIZE,
91 l1_cache_acs_cnt_int_ena: L1_CACHE_ACS_CNT_INT_ENA,
92 l1_cache_acs_cnt_int_clr: L1_CACHE_ACS_CNT_INT_CLR,
93 l1_cache_acs_cnt_int_raw: L1_CACHE_ACS_CNT_INT_RAW,
94 l1_cache_acs_cnt_int_st: L1_CACHE_ACS_CNT_INT_ST,
95 l1_cache_acs_fail_ctrl: L1_CACHE_ACS_FAIL_CTRL,
96 l1_cache_acs_fail_int_ena: L1_CACHE_ACS_FAIL_INT_ENA,
97 l1_cache_acs_fail_int_clr: L1_CACHE_ACS_FAIL_INT_CLR,
98 l1_cache_acs_fail_int_raw: L1_CACHE_ACS_FAIL_INT_RAW,
99 l1_cache_acs_fail_int_st: L1_CACHE_ACS_FAIL_INT_ST,
100 l1_cache_acs_cnt_ctrl: L1_CACHE_ACS_CNT_CTRL,
101 l1_ibus0_acs_hit_cnt: L1_IBUS0_ACS_HIT_CNT,
102 l1_ibus0_acs_miss_cnt: L1_IBUS0_ACS_MISS_CNT,
103 l1_ibus0_acs_conflict_cnt: L1_IBUS0_ACS_CONFLICT_CNT,
104 l1_ibus0_acs_nxtlvl_rd_cnt: L1_IBUS0_ACS_NXTLVL_RD_CNT,
105 l1_ibus1_acs_hit_cnt: L1_IBUS1_ACS_HIT_CNT,
106 l1_ibus1_acs_miss_cnt: L1_IBUS1_ACS_MISS_CNT,
107 l1_ibus1_acs_conflict_cnt: L1_IBUS1_ACS_CONFLICT_CNT,
108 l1_ibus1_acs_nxtlvl_rd_cnt: L1_IBUS1_ACS_NXTLVL_RD_CNT,
109 l1_ibus2_acs_hit_cnt: L1_IBUS2_ACS_HIT_CNT,
110 l1_ibus2_acs_miss_cnt: L1_IBUS2_ACS_MISS_CNT,
111 l1_ibus2_acs_conflict_cnt: L1_IBUS2_ACS_CONFLICT_CNT,
112 l1_ibus2_acs_nxtlvl_rd_cnt: L1_IBUS2_ACS_NXTLVL_RD_CNT,
113 l1_ibus3_acs_hit_cnt: L1_IBUS3_ACS_HIT_CNT,
114 l1_ibus3_acs_miss_cnt: L1_IBUS3_ACS_MISS_CNT,
115 l1_ibus3_acs_conflict_cnt: L1_IBUS3_ACS_CONFLICT_CNT,
116 l1_ibus3_acs_nxtlvl_rd_cnt: L1_IBUS3_ACS_NXTLVL_RD_CNT,
117 l1_dbus0_acs_hit_cnt: L1_DBUS0_ACS_HIT_CNT,
118 l1_dbus0_acs_miss_cnt: L1_DBUS0_ACS_MISS_CNT,
119 l1_dbus0_acs_conflict_cnt: L1_DBUS0_ACS_CONFLICT_CNT,
120 l1_dbus0_acs_nxtlvl_rd_cnt: L1_DBUS0_ACS_NXTLVL_RD_CNT,
121 l1_dbus0_acs_nxtlvl_wr_cnt: L1_DBUS0_ACS_NXTLVL_WR_CNT,
122 l1_dbus1_acs_hit_cnt: L1_DBUS1_ACS_HIT_CNT,
123 l1_dbus1_acs_miss_cnt: L1_DBUS1_ACS_MISS_CNT,
124 l1_dbus1_acs_conflict_cnt: L1_DBUS1_ACS_CONFLICT_CNT,
125 l1_dbus1_acs_nxtlvl_rd_cnt: L1_DBUS1_ACS_NXTLVL_RD_CNT,
126 l1_dbus1_acs_nxtlvl_wr_cnt: L1_DBUS1_ACS_NXTLVL_WR_CNT,
127 l1_dbus2_acs_hit_cnt: L1_DBUS2_ACS_HIT_CNT,
128 l1_dbus2_acs_miss_cnt: L1_DBUS2_ACS_MISS_CNT,
129 l1_dbus2_acs_conflict_cnt: L1_DBUS2_ACS_CONFLICT_CNT,
130 l1_dbus2_acs_nxtlvl_rd_cnt: L1_DBUS2_ACS_NXTLVL_RD_CNT,
131 l1_dbus2_acs_nxtlvl_wr_cnt: L1_DBUS2_ACS_NXTLVL_WR_CNT,
132 l1_dbus3_acs_hit_cnt: L1_DBUS3_ACS_HIT_CNT,
133 l1_dbus3_acs_miss_cnt: L1_DBUS3_ACS_MISS_CNT,
134 l1_dbus3_acs_conflict_cnt: L1_DBUS3_ACS_CONFLICT_CNT,
135 l1_dbus3_acs_nxtlvl_rd_cnt: L1_DBUS3_ACS_NXTLVL_RD_CNT,
136 l1_dbus3_acs_nxtlvl_wr_cnt: L1_DBUS3_ACS_NXTLVL_WR_CNT,
137 l1_icache0_acs_fail_id_attr: L1_ICACHE0_ACS_FAIL_ID_ATTR,
138 l1_icache0_acs_fail_addr: L1_ICACHE0_ACS_FAIL_ADDR,
139 l1_icache1_acs_fail_id_attr: L1_ICACHE1_ACS_FAIL_ID_ATTR,
140 l1_icache1_acs_fail_addr: L1_ICACHE1_ACS_FAIL_ADDR,
141 l1_icache2_acs_fail_id_attr: L1_ICACHE2_ACS_FAIL_ID_ATTR,
142 l1_icache2_acs_fail_addr: L1_ICACHE2_ACS_FAIL_ADDR,
143 l1_icache3_acs_fail_id_attr: L1_ICACHE3_ACS_FAIL_ID_ATTR,
144 l1_icache3_acs_fail_addr: L1_ICACHE3_ACS_FAIL_ADDR,
145 l1_dcache_acs_fail_id_attr: L1_DCACHE_ACS_FAIL_ID_ATTR,
146 l1_dcache_acs_fail_addr: L1_DCACHE_ACS_FAIL_ADDR,
147 sync_l1_cache_preload_int_ena: SYNC_L1_CACHE_PRELOAD_INT_ENA,
148 sync_l1_cache_preload_int_clr: SYNC_L1_CACHE_PRELOAD_INT_CLR,
149 sync_l1_cache_preload_int_raw: SYNC_L1_CACHE_PRELOAD_INT_RAW,
150 sync_l1_cache_preload_int_st: SYNC_L1_CACHE_PRELOAD_INT_ST,
151 sync_l1_cache_preload_exception: SYNC_L1_CACHE_PRELOAD_EXCEPTION,
152 l1_cache_sync_rst_ctrl: L1_CACHE_SYNC_RST_CTRL,
153 l1_cache_preload_rst_ctrl: L1_CACHE_PRELOAD_RST_CTRL,
154 l1_cache_autoload_buf_clr_ctrl: L1_CACHE_AUTOLOAD_BUF_CLR_CTRL,
155 l1_unallocate_buffer_clear: L1_UNALLOCATE_BUFFER_CLEAR,
156 l1_cache_object_ctrl: L1_CACHE_OBJECT_CTRL,
157 l1_cache_way_object: L1_CACHE_WAY_OBJECT,
158 l1_cache_vaddr: L1_CACHE_VADDR,
159 l1_cache_debug_bus: L1_CACHE_DEBUG_BUS,
160 level_split0: LEVEL_SPLIT0,
161 l2_cache_ctrl: L2_CACHE_CTRL,
162 l2_bypass_cache_conf: L2_BYPASS_CACHE_CONF,
163 l2_cache_cachesize_conf: L2_CACHE_CACHESIZE_CONF,
164 l2_cache_blocksize_conf: L2_CACHE_BLOCKSIZE_CONF,
165 l2_cache_wrap_around_ctrl: L2_CACHE_WRAP_AROUND_CTRL,
166 l2_cache_tag_mem_power_ctrl: L2_CACHE_TAG_MEM_POWER_CTRL,
167 l2_cache_data_mem_power_ctrl: L2_CACHE_DATA_MEM_POWER_CTRL,
168 l2_cache_freeze_ctrl: L2_CACHE_FREEZE_CTRL,
169 l2_cache_data_mem_acs_conf: L2_CACHE_DATA_MEM_ACS_CONF,
170 l2_cache_tag_mem_acs_conf: L2_CACHE_TAG_MEM_ACS_CONF,
171 l2_cache_prelock_conf: L2_CACHE_PRELOCK_CONF,
172 l2_cache_prelock_sct0_addr: L2_CACHE_PRELOCK_SCT0_ADDR,
173 l2_cache_prelock_sct1_addr: L2_CACHE_PRELOCK_SCT1_ADDR,
174 l2_cache_prelock_sct_size: L2_CACHE_PRELOCK_SCT_SIZE,
175 l2_cache_preload_ctrl: L2_CACHE_PRELOAD_CTRL,
176 l2_cache_preload_addr: L2_CACHE_PRELOAD_ADDR,
177 l2_cache_preload_size: L2_CACHE_PRELOAD_SIZE,
178 l2_cache_autoload_ctrl: L2_CACHE_AUTOLOAD_CTRL,
179 l2_cache_autoload_sct0_addr: L2_CACHE_AUTOLOAD_SCT0_ADDR,
180 l2_cache_autoload_sct0_size: L2_CACHE_AUTOLOAD_SCT0_SIZE,
181 l2_cache_autoload_sct1_addr: L2_CACHE_AUTOLOAD_SCT1_ADDR,
182 l2_cache_autoload_sct1_size: L2_CACHE_AUTOLOAD_SCT1_SIZE,
183 l2_cache_autoload_sct2_addr: L2_CACHE_AUTOLOAD_SCT2_ADDR,
184 l2_cache_autoload_sct2_size: L2_CACHE_AUTOLOAD_SCT2_SIZE,
185 l2_cache_autoload_sct3_addr: L2_CACHE_AUTOLOAD_SCT3_ADDR,
186 l2_cache_autoload_sct3_size: L2_CACHE_AUTOLOAD_SCT3_SIZE,
187 l2_cache_acs_cnt_int_ena: L2_CACHE_ACS_CNT_INT_ENA,
188 l2_cache_acs_cnt_int_clr: L2_CACHE_ACS_CNT_INT_CLR,
189 l2_cache_acs_cnt_int_raw: L2_CACHE_ACS_CNT_INT_RAW,
190 l2_cache_acs_cnt_int_st: L2_CACHE_ACS_CNT_INT_ST,
191 l2_cache_acs_fail_ctrl: L2_CACHE_ACS_FAIL_CTRL,
192 l2_cache_acs_fail_int_ena: L2_CACHE_ACS_FAIL_INT_ENA,
193 l2_cache_acs_fail_int_clr: L2_CACHE_ACS_FAIL_INT_CLR,
194 l2_cache_acs_fail_int_raw: L2_CACHE_ACS_FAIL_INT_RAW,
195 l2_cache_acs_fail_int_st: L2_CACHE_ACS_FAIL_INT_ST,
196 l2_cache_acs_cnt_ctrl: L2_CACHE_ACS_CNT_CTRL,
197 l2_ibus0_acs_hit_cnt: L2_IBUS0_ACS_HIT_CNT,
198 l2_ibus0_acs_miss_cnt: L2_IBUS0_ACS_MISS_CNT,
199 l2_ibus0_acs_conflict_cnt: L2_IBUS0_ACS_CONFLICT_CNT,
200 l2_ibus0_acs_nxtlvl_rd_cnt: L2_IBUS0_ACS_NXTLVL_RD_CNT,
201 l2_ibus1_acs_hit_cnt: L2_IBUS1_ACS_HIT_CNT,
202 l2_ibus1_acs_miss_cnt: L2_IBUS1_ACS_MISS_CNT,
203 l2_ibus1_acs_conflict_cnt: L2_IBUS1_ACS_CONFLICT_CNT,
204 l2_ibus1_acs_nxtlvl_rd_cnt: L2_IBUS1_ACS_NXTLVL_RD_CNT,
205 l2_ibus2_acs_hit_cnt: L2_IBUS2_ACS_HIT_CNT,
206 l2_ibus2_acs_miss_cnt: L2_IBUS2_ACS_MISS_CNT,
207 l2_ibus2_acs_conflict_cnt: L2_IBUS2_ACS_CONFLICT_CNT,
208 l2_ibus2_acs_nxtlvl_rd_cnt: L2_IBUS2_ACS_NXTLVL_RD_CNT,
209 l2_ibus3_acs_hit_cnt: L2_IBUS3_ACS_HIT_CNT,
210 l2_ibus3_acs_miss_cnt: L2_IBUS3_ACS_MISS_CNT,
211 l2_ibus3_acs_conflict_cnt: L2_IBUS3_ACS_CONFLICT_CNT,
212 l2_ibus3_acs_nxtlvl_rd_cnt: L2_IBUS3_ACS_NXTLVL_RD_CNT,
213 l2_dbus0_acs_hit_cnt: L2_DBUS0_ACS_HIT_CNT,
214 l2_dbus0_acs_miss_cnt: L2_DBUS0_ACS_MISS_CNT,
215 l2_dbus0_acs_conflict_cnt: L2_DBUS0_ACS_CONFLICT_CNT,
216 l2_dbus0_acs_nxtlvl_rd_cnt: L2_DBUS0_ACS_NXTLVL_RD_CNT,
217 l2_dbus0_acs_nxtlvl_wr_cnt: L2_DBUS0_ACS_NXTLVL_WR_CNT,
218 l2_dbus1_acs_hit_cnt: L2_DBUS1_ACS_HIT_CNT,
219 l2_dbus1_acs_miss_cnt: L2_DBUS1_ACS_MISS_CNT,
220 l2_dbus1_acs_conflict_cnt: L2_DBUS1_ACS_CONFLICT_CNT,
221 l2_dbus1_acs_nxtlvl_rd_cnt: L2_DBUS1_ACS_NXTLVL_RD_CNT,
222 l2_dbus1_acs_nxtlvl_wr_cnt: L2_DBUS1_ACS_NXTLVL_WR_CNT,
223 l2_dbus2_acs_hit_cnt: L2_DBUS2_ACS_HIT_CNT,
224 l2_dbus2_acs_miss_cnt: L2_DBUS2_ACS_MISS_CNT,
225 l2_dbus2_acs_conflict_cnt: L2_DBUS2_ACS_CONFLICT_CNT,
226 l2_dbus2_acs_nxtlvl_rd_cnt: L2_DBUS2_ACS_NXTLVL_RD_CNT,
227 l2_dbus2_acs_nxtlvl_wr_cnt: L2_DBUS2_ACS_NXTLVL_WR_CNT,
228 l2_dbus3_acs_hit_cnt: L2_DBUS3_ACS_HIT_CNT,
229 l2_dbus3_acs_miss_cnt: L2_DBUS3_ACS_MISS_CNT,
230 l2_dbus3_acs_conflict_cnt: L2_DBUS3_ACS_CONFLICT_CNT,
231 l2_dbus3_acs_nxtlvl_rd_cnt: L2_DBUS3_ACS_NXTLVL_RD_CNT,
232 l2_dbus3_acs_nxtlvl_wr_cnt: L2_DBUS3_ACS_NXTLVL_WR_CNT,
233 l2_cache_acs_fail_id_attr: L2_CACHE_ACS_FAIL_ID_ATTR,
234 l2_cache_acs_fail_addr: L2_CACHE_ACS_FAIL_ADDR,
235 l2_cache_sync_preload_int_ena: L2_CACHE_SYNC_PRELOAD_INT_ENA,
236 l2_cache_sync_preload_int_clr: L2_CACHE_SYNC_PRELOAD_INT_CLR,
237 l2_cache_sync_preload_int_raw: L2_CACHE_SYNC_PRELOAD_INT_RAW,
238 l2_cache_sync_preload_int_st: L2_CACHE_SYNC_PRELOAD_INT_ST,
239 l2_cache_sync_preload_exception: L2_CACHE_SYNC_PRELOAD_EXCEPTION,
240 l2_cache_sync_rst_ctrl: L2_CACHE_SYNC_RST_CTRL,
241 l2_cache_preload_rst_ctrl: L2_CACHE_PRELOAD_RST_CTRL,
242 l2_cache_autoload_buf_clr_ctrl: L2_CACHE_AUTOLOAD_BUF_CLR_CTRL,
243 l2_unallocate_buffer_clear: L2_UNALLOCATE_BUFFER_CLEAR,
244 l2_cache_access_attr_ctrl: L2_CACHE_ACCESS_ATTR_CTRL,
245 l2_cache_object_ctrl: L2_CACHE_OBJECT_CTRL,
246 l2_cache_way_object: L2_CACHE_WAY_OBJECT,
247 l2_cache_vaddr: L2_CACHE_VADDR,
248 l2_cache_debug_bus: L2_CACHE_DEBUG_BUS,
249 level_split1: LEVEL_SPLIT1,
250 clock_gate: CLOCK_GATE,
251 redundancy_sig0: REDUNDANCY_SIG0,
252 redundancy_sig1: REDUNDANCY_SIG1,
253 redundancy_sig2: REDUNDANCY_SIG2,
254 redundancy_sig3: REDUNDANCY_SIG3,
255 redundancy_sig4: REDUNDANCY_SIG4,
256 _reserved251: [u8; 0x10],
257 date: DATE,
258}
259impl RegisterBlock {
260 #[doc = "0x00 - L1 instruction Cache(L1-ICache) control register"]
261 #[inline(always)]
262 pub const fn l1_icache_ctrl(&self) -> &L1_ICACHE_CTRL {
263 &self.l1_icache_ctrl
264 }
265 #[doc = "0x04 - L1 data Cache(L1-DCache) control register"]
266 #[inline(always)]
267 pub const fn l1_dcache_ctrl(&self) -> &L1_DCACHE_CTRL {
268 &self.l1_dcache_ctrl
269 }
270 #[doc = "0x08 - Bypass Cache configure register"]
271 #[inline(always)]
272 pub const fn l1_bypass_cache_conf(&self) -> &L1_BYPASS_CACHE_CONF {
273 &self.l1_bypass_cache_conf
274 }
275 #[doc = "0x0c - L1 Cache atomic feature configure register"]
276 #[inline(always)]
277 pub const fn l1_cache_atomic_conf(&self) -> &L1_CACHE_ATOMIC_CONF {
278 &self.l1_cache_atomic_conf
279 }
280 #[doc = "0x10 - L1 instruction Cache CacheSize mode configure register"]
281 #[inline(always)]
282 pub const fn l1_icache_cachesize_conf(&self) -> &L1_ICACHE_CACHESIZE_CONF {
283 &self.l1_icache_cachesize_conf
284 }
285 #[doc = "0x14 - L1 instruction Cache BlockSize mode configure register"]
286 #[inline(always)]
287 pub const fn l1_icache_blocksize_conf(&self) -> &L1_ICACHE_BLOCKSIZE_CONF {
288 &self.l1_icache_blocksize_conf
289 }
290 #[doc = "0x18 - L1 data Cache CacheSize mode configure register"]
291 #[inline(always)]
292 pub const fn l1_dcache_cachesize_conf(&self) -> &L1_DCACHE_CACHESIZE_CONF {
293 &self.l1_dcache_cachesize_conf
294 }
295 #[doc = "0x1c - L1 data Cache BlockSize mode configure register"]
296 #[inline(always)]
297 pub const fn l1_dcache_blocksize_conf(&self) -> &L1_DCACHE_BLOCKSIZE_CONF {
298 &self.l1_dcache_blocksize_conf
299 }
300 #[doc = "0x20 - Cache wrap around control register"]
301 #[inline(always)]
302 pub const fn l1_cache_wrap_around_ctrl(&self) -> &L1_CACHE_WRAP_AROUND_CTRL {
303 &self.l1_cache_wrap_around_ctrl
304 }
305 #[doc = "0x24 - Cache tag memory power control register"]
306 #[inline(always)]
307 pub const fn l1_cache_tag_mem_power_ctrl(&self) -> &L1_CACHE_TAG_MEM_POWER_CTRL {
308 &self.l1_cache_tag_mem_power_ctrl
309 }
310 #[doc = "0x28 - Cache data memory power control register"]
311 #[inline(always)]
312 pub const fn l1_cache_data_mem_power_ctrl(&self) -> &L1_CACHE_DATA_MEM_POWER_CTRL {
313 &self.l1_cache_data_mem_power_ctrl
314 }
315 #[doc = "0x2c - Cache Freeze control register"]
316 #[inline(always)]
317 pub const fn l1_cache_freeze_ctrl(&self) -> &L1_CACHE_FREEZE_CTRL {
318 &self.l1_cache_freeze_ctrl
319 }
320 #[doc = "0x30 - Cache data memory access configure register"]
321 #[inline(always)]
322 pub const fn l1_cache_data_mem_acs_conf(&self) -> &L1_CACHE_DATA_MEM_ACS_CONF {
323 &self.l1_cache_data_mem_acs_conf
324 }
325 #[doc = "0x34 - Cache tag memory access configure register"]
326 #[inline(always)]
327 pub const fn l1_cache_tag_mem_acs_conf(&self) -> &L1_CACHE_TAG_MEM_ACS_CONF {
328 &self.l1_cache_tag_mem_acs_conf
329 }
330 #[doc = "0x38 - L1 instruction Cache 0 prelock configure register"]
331 #[inline(always)]
332 pub const fn l1_icache0_prelock_conf(&self) -> &L1_ICACHE0_PRELOCK_CONF {
333 &self.l1_icache0_prelock_conf
334 }
335 #[doc = "0x3c - L1 instruction Cache 0 prelock section0 address configure register"]
336 #[inline(always)]
337 pub const fn l1_icache0_prelock_sct0_addr(&self) -> &L1_ICACHE0_PRELOCK_SCT0_ADDR {
338 &self.l1_icache0_prelock_sct0_addr
339 }
340 #[doc = "0x40 - L1 instruction Cache 0 prelock section1 address configure register"]
341 #[inline(always)]
342 pub const fn l1_icache0_prelock_sct1_addr(&self) -> &L1_ICACHE0_PRELOCK_SCT1_ADDR {
343 &self.l1_icache0_prelock_sct1_addr
344 }
345 #[doc = "0x44 - L1 instruction Cache 0 prelock section size configure register"]
346 #[inline(always)]
347 pub const fn l1_icache0_prelock_sct_size(&self) -> &L1_ICACHE0_PRELOCK_SCT_SIZE {
348 &self.l1_icache0_prelock_sct_size
349 }
350 #[doc = "0x48 - L1 instruction Cache 1 prelock configure register"]
351 #[inline(always)]
352 pub const fn l1_icache1_prelock_conf(&self) -> &L1_ICACHE1_PRELOCK_CONF {
353 &self.l1_icache1_prelock_conf
354 }
355 #[doc = "0x4c - L1 instruction Cache 1 prelock section0 address configure register"]
356 #[inline(always)]
357 pub const fn l1_icache1_prelock_sct0_addr(&self) -> &L1_ICACHE1_PRELOCK_SCT0_ADDR {
358 &self.l1_icache1_prelock_sct0_addr
359 }
360 #[doc = "0x50 - L1 instruction Cache 1 prelock section1 address configure register"]
361 #[inline(always)]
362 pub const fn l1_icache1_prelock_sct1_addr(&self) -> &L1_ICACHE1_PRELOCK_SCT1_ADDR {
363 &self.l1_icache1_prelock_sct1_addr
364 }
365 #[doc = "0x54 - L1 instruction Cache 1 prelock section size configure register"]
366 #[inline(always)]
367 pub const fn l1_icache1_prelock_sct_size(&self) -> &L1_ICACHE1_PRELOCK_SCT_SIZE {
368 &self.l1_icache1_prelock_sct_size
369 }
370 #[doc = "0x58 - L1 instruction Cache 2 prelock configure register"]
371 #[inline(always)]
372 pub const fn l1_icache2_prelock_conf(&self) -> &L1_ICACHE2_PRELOCK_CONF {
373 &self.l1_icache2_prelock_conf
374 }
375 #[doc = "0x5c - L1 instruction Cache 2 prelock section0 address configure register"]
376 #[inline(always)]
377 pub const fn l1_icache2_prelock_sct0_addr(&self) -> &L1_ICACHE2_PRELOCK_SCT0_ADDR {
378 &self.l1_icache2_prelock_sct0_addr
379 }
380 #[doc = "0x60 - L1 instruction Cache 2 prelock section1 address configure register"]
381 #[inline(always)]
382 pub const fn l1_icache2_prelock_sct1_addr(&self) -> &L1_ICACHE2_PRELOCK_SCT1_ADDR {
383 &self.l1_icache2_prelock_sct1_addr
384 }
385 #[doc = "0x64 - L1 instruction Cache 2 prelock section size configure register"]
386 #[inline(always)]
387 pub const fn l1_icache2_prelock_sct_size(&self) -> &L1_ICACHE2_PRELOCK_SCT_SIZE {
388 &self.l1_icache2_prelock_sct_size
389 }
390 #[doc = "0x68 - L1 instruction Cache 3 prelock configure register"]
391 #[inline(always)]
392 pub const fn l1_icache3_prelock_conf(&self) -> &L1_ICACHE3_PRELOCK_CONF {
393 &self.l1_icache3_prelock_conf
394 }
395 #[doc = "0x6c - L1 instruction Cache 3 prelock section0 address configure register"]
396 #[inline(always)]
397 pub const fn l1_icache3_prelock_sct0_addr(&self) -> &L1_ICACHE3_PRELOCK_SCT0_ADDR {
398 &self.l1_icache3_prelock_sct0_addr
399 }
400 #[doc = "0x70 - L1 instruction Cache 3 prelock section1 address configure register"]
401 #[inline(always)]
402 pub const fn l1_icache3_prelock_sct1_addr(&self) -> &L1_ICACHE3_PRELOCK_SCT1_ADDR {
403 &self.l1_icache3_prelock_sct1_addr
404 }
405 #[doc = "0x74 - L1 instruction Cache 3 prelock section size configure register"]
406 #[inline(always)]
407 pub const fn l1_icache3_prelock_sct_size(&self) -> &L1_ICACHE3_PRELOCK_SCT_SIZE {
408 &self.l1_icache3_prelock_sct_size
409 }
410 #[doc = "0x78 - L1 data Cache prelock configure register"]
411 #[inline(always)]
412 pub const fn l1_dcache_prelock_conf(&self) -> &L1_DCACHE_PRELOCK_CONF {
413 &self.l1_dcache_prelock_conf
414 }
415 #[doc = "0x7c - L1 data Cache prelock section0 address configure register"]
416 #[inline(always)]
417 pub const fn l1_dcache_prelock_sct0_addr(&self) -> &L1_DCACHE_PRELOCK_SCT0_ADDR {
418 &self.l1_dcache_prelock_sct0_addr
419 }
420 #[doc = "0x80 - L1 data Cache prelock section1 address configure register"]
421 #[inline(always)]
422 pub const fn l1_dcache_prelock_sct1_addr(&self) -> &L1_DCACHE_PRELOCK_SCT1_ADDR {
423 &self.l1_dcache_prelock_sct1_addr
424 }
425 #[doc = "0x84 - L1 data Cache prelock section size configure register"]
426 #[inline(always)]
427 pub const fn l1_dcache_prelock_sct_size(&self) -> &L1_DCACHE_PRELOCK_SCT_SIZE {
428 &self.l1_dcache_prelock_sct_size
429 }
430 #[doc = "0x88 - Lock-class (manual lock) operation control register"]
431 #[inline(always)]
432 pub const fn lock_ctrl(&self) -> &LOCK_CTRL {
433 &self.lock_ctrl
434 }
435 #[doc = "0x8c - Lock (manual lock) map configure register"]
436 #[inline(always)]
437 pub const fn lock_map(&self) -> &LOCK_MAP {
438 &self.lock_map
439 }
440 #[doc = "0x90 - Lock (manual lock) address configure register"]
441 #[inline(always)]
442 pub const fn lock_addr(&self) -> &LOCK_ADDR {
443 &self.lock_addr
444 }
445 #[doc = "0x94 - Lock (manual lock) size configure register"]
446 #[inline(always)]
447 pub const fn lock_size(&self) -> &LOCK_SIZE {
448 &self.lock_size
449 }
450 #[doc = "0x98 - Sync-class operation control register"]
451 #[inline(always)]
452 pub const fn sync_ctrl(&self) -> &SYNC_CTRL {
453 &self.sync_ctrl
454 }
455 #[doc = "0x9c - Sync map configure register"]
456 #[inline(always)]
457 pub const fn sync_map(&self) -> &SYNC_MAP {
458 &self.sync_map
459 }
460 #[doc = "0xa0 - Sync address configure register"]
461 #[inline(always)]
462 pub const fn sync_addr(&self) -> &SYNC_ADDR {
463 &self.sync_addr
464 }
465 #[doc = "0xa4 - Sync size configure register"]
466 #[inline(always)]
467 pub const fn sync_size(&self) -> &SYNC_SIZE {
468 &self.sync_size
469 }
470 #[doc = "0xa8 - L1 instruction Cache 0 preload-operation control register"]
471 #[inline(always)]
472 pub const fn l1_icache0_preload_ctrl(&self) -> &L1_ICACHE0_PRELOAD_CTRL {
473 &self.l1_icache0_preload_ctrl
474 }
475 #[doc = "0xac - L1 instruction Cache 0 preload address configure register"]
476 #[inline(always)]
477 pub const fn l1_icache0_preload_addr(&self) -> &L1_ICACHE0_PRELOAD_ADDR {
478 &self.l1_icache0_preload_addr
479 }
480 #[doc = "0xb0 - L1 instruction Cache 0 preload size configure register"]
481 #[inline(always)]
482 pub const fn l1_icache0_preload_size(&self) -> &L1_ICACHE0_PRELOAD_SIZE {
483 &self.l1_icache0_preload_size
484 }
485 #[doc = "0xb4 - L1 instruction Cache 1 preload-operation control register"]
486 #[inline(always)]
487 pub const fn l1_icache1_preload_ctrl(&self) -> &L1_ICACHE1_PRELOAD_CTRL {
488 &self.l1_icache1_preload_ctrl
489 }
490 #[doc = "0xb8 - L1 instruction Cache 1 preload address configure register"]
491 #[inline(always)]
492 pub const fn l1_icache1_preload_addr(&self) -> &L1_ICACHE1_PRELOAD_ADDR {
493 &self.l1_icache1_preload_addr
494 }
495 #[doc = "0xbc - L1 instruction Cache 1 preload size configure register"]
496 #[inline(always)]
497 pub const fn l1_icache1_preload_size(&self) -> &L1_ICACHE1_PRELOAD_SIZE {
498 &self.l1_icache1_preload_size
499 }
500 #[doc = "0xc0 - L1 instruction Cache 2 preload-operation control register"]
501 #[inline(always)]
502 pub const fn l1_icache2_preload_ctrl(&self) -> &L1_ICACHE2_PRELOAD_CTRL {
503 &self.l1_icache2_preload_ctrl
504 }
505 #[doc = "0xc4 - L1 instruction Cache 2 preload address configure register"]
506 #[inline(always)]
507 pub const fn l1_icache2_preload_addr(&self) -> &L1_ICACHE2_PRELOAD_ADDR {
508 &self.l1_icache2_preload_addr
509 }
510 #[doc = "0xc8 - L1 instruction Cache 2 preload size configure register"]
511 #[inline(always)]
512 pub const fn l1_icache2_preload_size(&self) -> &L1_ICACHE2_PRELOAD_SIZE {
513 &self.l1_icache2_preload_size
514 }
515 #[doc = "0xcc - L1 instruction Cache 3 preload-operation control register"]
516 #[inline(always)]
517 pub const fn l1_icache3_preload_ctrl(&self) -> &L1_ICACHE3_PRELOAD_CTRL {
518 &self.l1_icache3_preload_ctrl
519 }
520 #[doc = "0xd0 - L1 instruction Cache 3 preload address configure register"]
521 #[inline(always)]
522 pub const fn l1_icache3_preload_addr(&self) -> &L1_ICACHE3_PRELOAD_ADDR {
523 &self.l1_icache3_preload_addr
524 }
525 #[doc = "0xd4 - L1 instruction Cache 3 preload size configure register"]
526 #[inline(always)]
527 pub const fn l1_icache3_preload_size(&self) -> &L1_ICACHE3_PRELOAD_SIZE {
528 &self.l1_icache3_preload_size
529 }
530 #[doc = "0xd8 - L1 data Cache preload-operation control register"]
531 #[inline(always)]
532 pub const fn l1_dcache_preload_ctrl(&self) -> &L1_DCACHE_PRELOAD_CTRL {
533 &self.l1_dcache_preload_ctrl
534 }
535 #[doc = "0xdc - L1 data Cache preload address configure register"]
536 #[inline(always)]
537 pub const fn l1_dcache_preload_addr(&self) -> &L1_DCACHE_PRELOAD_ADDR {
538 &self.l1_dcache_preload_addr
539 }
540 #[doc = "0xe0 - L1 data Cache preload size configure register"]
541 #[inline(always)]
542 pub const fn l1_dcache_preload_size(&self) -> &L1_DCACHE_PRELOAD_SIZE {
543 &self.l1_dcache_preload_size
544 }
545 #[doc = "0xe4 - L1 instruction Cache 0 autoload-operation control register"]
546 #[inline(always)]
547 pub const fn l1_icache0_autoload_ctrl(&self) -> &L1_ICACHE0_AUTOLOAD_CTRL {
548 &self.l1_icache0_autoload_ctrl
549 }
550 #[doc = "0xe8 - L1 instruction Cache 0 autoload section 0 address configure register"]
551 #[inline(always)]
552 pub const fn l1_icache0_autoload_sct0_addr(&self) -> &L1_ICACHE0_AUTOLOAD_SCT0_ADDR {
553 &self.l1_icache0_autoload_sct0_addr
554 }
555 #[doc = "0xec - L1 instruction Cache 0 autoload section 0 size configure register"]
556 #[inline(always)]
557 pub const fn l1_icache0_autoload_sct0_size(&self) -> &L1_ICACHE0_AUTOLOAD_SCT0_SIZE {
558 &self.l1_icache0_autoload_sct0_size
559 }
560 #[doc = "0xf0 - L1 instruction Cache 0 autoload section 1 address configure register"]
561 #[inline(always)]
562 pub const fn l1_icache0_autoload_sct1_addr(&self) -> &L1_ICACHE0_AUTOLOAD_SCT1_ADDR {
563 &self.l1_icache0_autoload_sct1_addr
564 }
565 #[doc = "0xf4 - L1 instruction Cache 0 autoload section 1 size configure register"]
566 #[inline(always)]
567 pub const fn l1_icache0_autoload_sct1_size(&self) -> &L1_ICACHE0_AUTOLOAD_SCT1_SIZE {
568 &self.l1_icache0_autoload_sct1_size
569 }
570 #[doc = "0xf8 - L1 instruction Cache 1 autoload-operation control register"]
571 #[inline(always)]
572 pub const fn l1_icache1_autoload_ctrl(&self) -> &L1_ICACHE1_AUTOLOAD_CTRL {
573 &self.l1_icache1_autoload_ctrl
574 }
575 #[doc = "0xfc - L1 instruction Cache 1 autoload section 0 address configure register"]
576 #[inline(always)]
577 pub const fn l1_icache1_autoload_sct0_addr(&self) -> &L1_ICACHE1_AUTOLOAD_SCT0_ADDR {
578 &self.l1_icache1_autoload_sct0_addr
579 }
580 #[doc = "0x100 - L1 instruction Cache 1 autoload section 0 size configure register"]
581 #[inline(always)]
582 pub const fn l1_icache1_autoload_sct0_size(&self) -> &L1_ICACHE1_AUTOLOAD_SCT0_SIZE {
583 &self.l1_icache1_autoload_sct0_size
584 }
585 #[doc = "0x104 - L1 instruction Cache 1 autoload section 1 address configure register"]
586 #[inline(always)]
587 pub const fn l1_icache1_autoload_sct1_addr(&self) -> &L1_ICACHE1_AUTOLOAD_SCT1_ADDR {
588 &self.l1_icache1_autoload_sct1_addr
589 }
590 #[doc = "0x108 - L1 instruction Cache 1 autoload section 1 size configure register"]
591 #[inline(always)]
592 pub const fn l1_icache1_autoload_sct1_size(&self) -> &L1_ICACHE1_AUTOLOAD_SCT1_SIZE {
593 &self.l1_icache1_autoload_sct1_size
594 }
595 #[doc = "0x10c - L1 instruction Cache 2 autoload-operation control register"]
596 #[inline(always)]
597 pub const fn l1_icache2_autoload_ctrl(&self) -> &L1_ICACHE2_AUTOLOAD_CTRL {
598 &self.l1_icache2_autoload_ctrl
599 }
600 #[doc = "0x110 - L1 instruction Cache 2 autoload section 0 address configure register"]
601 #[inline(always)]
602 pub const fn l1_icache2_autoload_sct0_addr(&self) -> &L1_ICACHE2_AUTOLOAD_SCT0_ADDR {
603 &self.l1_icache2_autoload_sct0_addr
604 }
605 #[doc = "0x114 - L1 instruction Cache 2 autoload section 0 size configure register"]
606 #[inline(always)]
607 pub const fn l1_icache2_autoload_sct0_size(&self) -> &L1_ICACHE2_AUTOLOAD_SCT0_SIZE {
608 &self.l1_icache2_autoload_sct0_size
609 }
610 #[doc = "0x118 - L1 instruction Cache 2 autoload section 1 address configure register"]
611 #[inline(always)]
612 pub const fn l1_icache2_autoload_sct1_addr(&self) -> &L1_ICACHE2_AUTOLOAD_SCT1_ADDR {
613 &self.l1_icache2_autoload_sct1_addr
614 }
615 #[doc = "0x11c - L1 instruction Cache 2 autoload section 1 size configure register"]
616 #[inline(always)]
617 pub const fn l1_icache2_autoload_sct1_size(&self) -> &L1_ICACHE2_AUTOLOAD_SCT1_SIZE {
618 &self.l1_icache2_autoload_sct1_size
619 }
620 #[doc = "0x120 - L1 instruction Cache 3 autoload-operation control register"]
621 #[inline(always)]
622 pub const fn l1_icache3_autoload_ctrl(&self) -> &L1_ICACHE3_AUTOLOAD_CTRL {
623 &self.l1_icache3_autoload_ctrl
624 }
625 #[doc = "0x124 - L1 instruction Cache 3 autoload section 0 address configure register"]
626 #[inline(always)]
627 pub const fn l1_icache3_autoload_sct0_addr(&self) -> &L1_ICACHE3_AUTOLOAD_SCT0_ADDR {
628 &self.l1_icache3_autoload_sct0_addr
629 }
630 #[doc = "0x128 - L1 instruction Cache 3 autoload section 0 size configure register"]
631 #[inline(always)]
632 pub const fn l1_icache3_autoload_sct0_size(&self) -> &L1_ICACHE3_AUTOLOAD_SCT0_SIZE {
633 &self.l1_icache3_autoload_sct0_size
634 }
635 #[doc = "0x12c - L1 instruction Cache 3 autoload section 1 address configure register"]
636 #[inline(always)]
637 pub const fn l1_icache3_autoload_sct1_addr(&self) -> &L1_ICACHE3_AUTOLOAD_SCT1_ADDR {
638 &self.l1_icache3_autoload_sct1_addr
639 }
640 #[doc = "0x130 - L1 instruction Cache 3 autoload section 1 size configure register"]
641 #[inline(always)]
642 pub const fn l1_icache3_autoload_sct1_size(&self) -> &L1_ICACHE3_AUTOLOAD_SCT1_SIZE {
643 &self.l1_icache3_autoload_sct1_size
644 }
645 #[doc = "0x134 - L1 data Cache autoload-operation control register"]
646 #[inline(always)]
647 pub const fn l1_dcache_autoload_ctrl(&self) -> &L1_DCACHE_AUTOLOAD_CTRL {
648 &self.l1_dcache_autoload_ctrl
649 }
650 #[doc = "0x138 - L1 data Cache autoload section 0 address configure register"]
651 #[inline(always)]
652 pub const fn l1_dcache_autoload_sct0_addr(&self) -> &L1_DCACHE_AUTOLOAD_SCT0_ADDR {
653 &self.l1_dcache_autoload_sct0_addr
654 }
655 #[doc = "0x13c - L1 data Cache autoload section 0 size configure register"]
656 #[inline(always)]
657 pub const fn l1_dcache_autoload_sct0_size(&self) -> &L1_DCACHE_AUTOLOAD_SCT0_SIZE {
658 &self.l1_dcache_autoload_sct0_size
659 }
660 #[doc = "0x140 - L1 data Cache autoload section 1 address configure register"]
661 #[inline(always)]
662 pub const fn l1_dcache_autoload_sct1_addr(&self) -> &L1_DCACHE_AUTOLOAD_SCT1_ADDR {
663 &self.l1_dcache_autoload_sct1_addr
664 }
665 #[doc = "0x144 - L1 data Cache autoload section 1 size configure register"]
666 #[inline(always)]
667 pub const fn l1_dcache_autoload_sct1_size(&self) -> &L1_DCACHE_AUTOLOAD_SCT1_SIZE {
668 &self.l1_dcache_autoload_sct1_size
669 }
670 #[doc = "0x148 - L1 data Cache autoload section 2 address configure register"]
671 #[inline(always)]
672 pub const fn l1_dcache_autoload_sct2_addr(&self) -> &L1_DCACHE_AUTOLOAD_SCT2_ADDR {
673 &self.l1_dcache_autoload_sct2_addr
674 }
675 #[doc = "0x14c - L1 data Cache autoload section 2 size configure register"]
676 #[inline(always)]
677 pub const fn l1_dcache_autoload_sct2_size(&self) -> &L1_DCACHE_AUTOLOAD_SCT2_SIZE {
678 &self.l1_dcache_autoload_sct2_size
679 }
680 #[doc = "0x150 - L1 data Cache autoload section 1 address configure register"]
681 #[inline(always)]
682 pub const fn l1_dcache_autoload_sct3_addr(&self) -> &L1_DCACHE_AUTOLOAD_SCT3_ADDR {
683 &self.l1_dcache_autoload_sct3_addr
684 }
685 #[doc = "0x154 - L1 data Cache autoload section 1 size configure register"]
686 #[inline(always)]
687 pub const fn l1_dcache_autoload_sct3_size(&self) -> &L1_DCACHE_AUTOLOAD_SCT3_SIZE {
688 &self.l1_dcache_autoload_sct3_size
689 }
690 #[doc = "0x158 - Cache Access Counter Interrupt enable register"]
691 #[inline(always)]
692 pub const fn l1_cache_acs_cnt_int_ena(&self) -> &L1_CACHE_ACS_CNT_INT_ENA {
693 &self.l1_cache_acs_cnt_int_ena
694 }
695 #[doc = "0x15c - Cache Access Counter Interrupt clear register"]
696 #[inline(always)]
697 pub const fn l1_cache_acs_cnt_int_clr(&self) -> &L1_CACHE_ACS_CNT_INT_CLR {
698 &self.l1_cache_acs_cnt_int_clr
699 }
700 #[doc = "0x160 - Cache Access Counter Interrupt raw register"]
701 #[inline(always)]
702 pub const fn l1_cache_acs_cnt_int_raw(&self) -> &L1_CACHE_ACS_CNT_INT_RAW {
703 &self.l1_cache_acs_cnt_int_raw
704 }
705 #[doc = "0x164 - Cache Access Counter Interrupt status register"]
706 #[inline(always)]
707 pub const fn l1_cache_acs_cnt_int_st(&self) -> &L1_CACHE_ACS_CNT_INT_ST {
708 &self.l1_cache_acs_cnt_int_st
709 }
710 #[doc = "0x168 - Cache Access Fail Configuration register"]
711 #[inline(always)]
712 pub const fn l1_cache_acs_fail_ctrl(&self) -> &L1_CACHE_ACS_FAIL_CTRL {
713 &self.l1_cache_acs_fail_ctrl
714 }
715 #[doc = "0x16c - Cache Access Fail Interrupt enable register"]
716 #[inline(always)]
717 pub const fn l1_cache_acs_fail_int_ena(&self) -> &L1_CACHE_ACS_FAIL_INT_ENA {
718 &self.l1_cache_acs_fail_int_ena
719 }
720 #[doc = "0x170 - L1-Cache Access Fail Interrupt clear register"]
721 #[inline(always)]
722 pub const fn l1_cache_acs_fail_int_clr(&self) -> &L1_CACHE_ACS_FAIL_INT_CLR {
723 &self.l1_cache_acs_fail_int_clr
724 }
725 #[doc = "0x174 - Cache Access Fail Interrupt raw register"]
726 #[inline(always)]
727 pub const fn l1_cache_acs_fail_int_raw(&self) -> &L1_CACHE_ACS_FAIL_INT_RAW {
728 &self.l1_cache_acs_fail_int_raw
729 }
730 #[doc = "0x178 - Cache Access Fail Interrupt status register"]
731 #[inline(always)]
732 pub const fn l1_cache_acs_fail_int_st(&self) -> &L1_CACHE_ACS_FAIL_INT_ST {
733 &self.l1_cache_acs_fail_int_st
734 }
735 #[doc = "0x17c - Cache Access Counter enable and clear register"]
736 #[inline(always)]
737 pub const fn l1_cache_acs_cnt_ctrl(&self) -> &L1_CACHE_ACS_CNT_CTRL {
738 &self.l1_cache_acs_cnt_ctrl
739 }
740 #[doc = "0x180 - L1-ICache bus0 Hit-Access Counter register"]
741 #[inline(always)]
742 pub const fn l1_ibus0_acs_hit_cnt(&self) -> &L1_IBUS0_ACS_HIT_CNT {
743 &self.l1_ibus0_acs_hit_cnt
744 }
745 #[doc = "0x184 - L1-ICache bus0 Miss-Access Counter register"]
746 #[inline(always)]
747 pub const fn l1_ibus0_acs_miss_cnt(&self) -> &L1_IBUS0_ACS_MISS_CNT {
748 &self.l1_ibus0_acs_miss_cnt
749 }
750 #[doc = "0x188 - L1-ICache bus0 Conflict-Access Counter register"]
751 #[inline(always)]
752 pub const fn l1_ibus0_acs_conflict_cnt(&self) -> &L1_IBUS0_ACS_CONFLICT_CNT {
753 &self.l1_ibus0_acs_conflict_cnt
754 }
755 #[doc = "0x18c - L1-ICache bus0 Next-Level-Access Counter register"]
756 #[inline(always)]
757 pub const fn l1_ibus0_acs_nxtlvl_rd_cnt(&self) -> &L1_IBUS0_ACS_NXTLVL_RD_CNT {
758 &self.l1_ibus0_acs_nxtlvl_rd_cnt
759 }
760 #[doc = "0x190 - L1-ICache bus1 Hit-Access Counter register"]
761 #[inline(always)]
762 pub const fn l1_ibus1_acs_hit_cnt(&self) -> &L1_IBUS1_ACS_HIT_CNT {
763 &self.l1_ibus1_acs_hit_cnt
764 }
765 #[doc = "0x194 - L1-ICache bus1 Miss-Access Counter register"]
766 #[inline(always)]
767 pub const fn l1_ibus1_acs_miss_cnt(&self) -> &L1_IBUS1_ACS_MISS_CNT {
768 &self.l1_ibus1_acs_miss_cnt
769 }
770 #[doc = "0x198 - L1-ICache bus1 Conflict-Access Counter register"]
771 #[inline(always)]
772 pub const fn l1_ibus1_acs_conflict_cnt(&self) -> &L1_IBUS1_ACS_CONFLICT_CNT {
773 &self.l1_ibus1_acs_conflict_cnt
774 }
775 #[doc = "0x19c - L1-ICache bus1 Next-Level-Access Counter register"]
776 #[inline(always)]
777 pub const fn l1_ibus1_acs_nxtlvl_rd_cnt(&self) -> &L1_IBUS1_ACS_NXTLVL_RD_CNT {
778 &self.l1_ibus1_acs_nxtlvl_rd_cnt
779 }
780 #[doc = "0x1a0 - L1-ICache bus2 Hit-Access Counter register"]
781 #[inline(always)]
782 pub const fn l1_ibus2_acs_hit_cnt(&self) -> &L1_IBUS2_ACS_HIT_CNT {
783 &self.l1_ibus2_acs_hit_cnt
784 }
785 #[doc = "0x1a4 - L1-ICache bus2 Miss-Access Counter register"]
786 #[inline(always)]
787 pub const fn l1_ibus2_acs_miss_cnt(&self) -> &L1_IBUS2_ACS_MISS_CNT {
788 &self.l1_ibus2_acs_miss_cnt
789 }
790 #[doc = "0x1a8 - L1-ICache bus2 Conflict-Access Counter register"]
791 #[inline(always)]
792 pub const fn l1_ibus2_acs_conflict_cnt(&self) -> &L1_IBUS2_ACS_CONFLICT_CNT {
793 &self.l1_ibus2_acs_conflict_cnt
794 }
795 #[doc = "0x1ac - L1-ICache bus2 Next-Level-Access Counter register"]
796 #[inline(always)]
797 pub const fn l1_ibus2_acs_nxtlvl_rd_cnt(&self) -> &L1_IBUS2_ACS_NXTLVL_RD_CNT {
798 &self.l1_ibus2_acs_nxtlvl_rd_cnt
799 }
800 #[doc = "0x1b0 - L1-ICache bus3 Hit-Access Counter register"]
801 #[inline(always)]
802 pub const fn l1_ibus3_acs_hit_cnt(&self) -> &L1_IBUS3_ACS_HIT_CNT {
803 &self.l1_ibus3_acs_hit_cnt
804 }
805 #[doc = "0x1b4 - L1-ICache bus3 Miss-Access Counter register"]
806 #[inline(always)]
807 pub const fn l1_ibus3_acs_miss_cnt(&self) -> &L1_IBUS3_ACS_MISS_CNT {
808 &self.l1_ibus3_acs_miss_cnt
809 }
810 #[doc = "0x1b8 - L1-ICache bus3 Conflict-Access Counter register"]
811 #[inline(always)]
812 pub const fn l1_ibus3_acs_conflict_cnt(&self) -> &L1_IBUS3_ACS_CONFLICT_CNT {
813 &self.l1_ibus3_acs_conflict_cnt
814 }
815 #[doc = "0x1bc - L1-ICache bus3 Next-Level-Access Counter register"]
816 #[inline(always)]
817 pub const fn l1_ibus3_acs_nxtlvl_rd_cnt(&self) -> &L1_IBUS3_ACS_NXTLVL_RD_CNT {
818 &self.l1_ibus3_acs_nxtlvl_rd_cnt
819 }
820 #[doc = "0x1c0 - L1-DCache bus0 Hit-Access Counter register"]
821 #[inline(always)]
822 pub const fn l1_dbus0_acs_hit_cnt(&self) -> &L1_DBUS0_ACS_HIT_CNT {
823 &self.l1_dbus0_acs_hit_cnt
824 }
825 #[doc = "0x1c4 - L1-DCache bus0 Miss-Access Counter register"]
826 #[inline(always)]
827 pub const fn l1_dbus0_acs_miss_cnt(&self) -> &L1_DBUS0_ACS_MISS_CNT {
828 &self.l1_dbus0_acs_miss_cnt
829 }
830 #[doc = "0x1c8 - L1-DCache bus0 Conflict-Access Counter register"]
831 #[inline(always)]
832 pub const fn l1_dbus0_acs_conflict_cnt(&self) -> &L1_DBUS0_ACS_CONFLICT_CNT {
833 &self.l1_dbus0_acs_conflict_cnt
834 }
835 #[doc = "0x1cc - L1-DCache bus0 Next-Level-Access Counter register"]
836 #[inline(always)]
837 pub const fn l1_dbus0_acs_nxtlvl_rd_cnt(&self) -> &L1_DBUS0_ACS_NXTLVL_RD_CNT {
838 &self.l1_dbus0_acs_nxtlvl_rd_cnt
839 }
840 #[doc = "0x1d0 - L1-DCache bus0 WB-Access Counter register"]
841 #[inline(always)]
842 pub const fn l1_dbus0_acs_nxtlvl_wr_cnt(&self) -> &L1_DBUS0_ACS_NXTLVL_WR_CNT {
843 &self.l1_dbus0_acs_nxtlvl_wr_cnt
844 }
845 #[doc = "0x1d4 - L1-DCache bus1 Hit-Access Counter register"]
846 #[inline(always)]
847 pub const fn l1_dbus1_acs_hit_cnt(&self) -> &L1_DBUS1_ACS_HIT_CNT {
848 &self.l1_dbus1_acs_hit_cnt
849 }
850 #[doc = "0x1d8 - L1-DCache bus1 Miss-Access Counter register"]
851 #[inline(always)]
852 pub const fn l1_dbus1_acs_miss_cnt(&self) -> &L1_DBUS1_ACS_MISS_CNT {
853 &self.l1_dbus1_acs_miss_cnt
854 }
855 #[doc = "0x1dc - L1-DCache bus1 Conflict-Access Counter register"]
856 #[inline(always)]
857 pub const fn l1_dbus1_acs_conflict_cnt(&self) -> &L1_DBUS1_ACS_CONFLICT_CNT {
858 &self.l1_dbus1_acs_conflict_cnt
859 }
860 #[doc = "0x1e0 - L1-DCache bus1 Next-Level-Access Counter register"]
861 #[inline(always)]
862 pub const fn l1_dbus1_acs_nxtlvl_rd_cnt(&self) -> &L1_DBUS1_ACS_NXTLVL_RD_CNT {
863 &self.l1_dbus1_acs_nxtlvl_rd_cnt
864 }
865 #[doc = "0x1e4 - L1-DCache bus1 WB-Access Counter register"]
866 #[inline(always)]
867 pub const fn l1_dbus1_acs_nxtlvl_wr_cnt(&self) -> &L1_DBUS1_ACS_NXTLVL_WR_CNT {
868 &self.l1_dbus1_acs_nxtlvl_wr_cnt
869 }
870 #[doc = "0x1e8 - L1-DCache bus2 Hit-Access Counter register"]
871 #[inline(always)]
872 pub const fn l1_dbus2_acs_hit_cnt(&self) -> &L1_DBUS2_ACS_HIT_CNT {
873 &self.l1_dbus2_acs_hit_cnt
874 }
875 #[doc = "0x1ec - L1-DCache bus2 Miss-Access Counter register"]
876 #[inline(always)]
877 pub const fn l1_dbus2_acs_miss_cnt(&self) -> &L1_DBUS2_ACS_MISS_CNT {
878 &self.l1_dbus2_acs_miss_cnt
879 }
880 #[doc = "0x1f0 - L1-DCache bus2 Conflict-Access Counter register"]
881 #[inline(always)]
882 pub const fn l1_dbus2_acs_conflict_cnt(&self) -> &L1_DBUS2_ACS_CONFLICT_CNT {
883 &self.l1_dbus2_acs_conflict_cnt
884 }
885 #[doc = "0x1f4 - L1-DCache bus2 Next-Level-Access Counter register"]
886 #[inline(always)]
887 pub const fn l1_dbus2_acs_nxtlvl_rd_cnt(&self) -> &L1_DBUS2_ACS_NXTLVL_RD_CNT {
888 &self.l1_dbus2_acs_nxtlvl_rd_cnt
889 }
890 #[doc = "0x1f8 - L1-DCache bus2 WB-Access Counter register"]
891 #[inline(always)]
892 pub const fn l1_dbus2_acs_nxtlvl_wr_cnt(&self) -> &L1_DBUS2_ACS_NXTLVL_WR_CNT {
893 &self.l1_dbus2_acs_nxtlvl_wr_cnt
894 }
895 #[doc = "0x1fc - L1-DCache bus3 Hit-Access Counter register"]
896 #[inline(always)]
897 pub const fn l1_dbus3_acs_hit_cnt(&self) -> &L1_DBUS3_ACS_HIT_CNT {
898 &self.l1_dbus3_acs_hit_cnt
899 }
900 #[doc = "0x200 - L1-DCache bus3 Miss-Access Counter register"]
901 #[inline(always)]
902 pub const fn l1_dbus3_acs_miss_cnt(&self) -> &L1_DBUS3_ACS_MISS_CNT {
903 &self.l1_dbus3_acs_miss_cnt
904 }
905 #[doc = "0x204 - L1-DCache bus3 Conflict-Access Counter register"]
906 #[inline(always)]
907 pub const fn l1_dbus3_acs_conflict_cnt(&self) -> &L1_DBUS3_ACS_CONFLICT_CNT {
908 &self.l1_dbus3_acs_conflict_cnt
909 }
910 #[doc = "0x208 - L1-DCache bus3 Next-Level-Access Counter register"]
911 #[inline(always)]
912 pub const fn l1_dbus3_acs_nxtlvl_rd_cnt(&self) -> &L1_DBUS3_ACS_NXTLVL_RD_CNT {
913 &self.l1_dbus3_acs_nxtlvl_rd_cnt
914 }
915 #[doc = "0x20c - L1-DCache bus3 WB-Access Counter register"]
916 #[inline(always)]
917 pub const fn l1_dbus3_acs_nxtlvl_wr_cnt(&self) -> &L1_DBUS3_ACS_NXTLVL_WR_CNT {
918 &self.l1_dbus3_acs_nxtlvl_wr_cnt
919 }
920 #[doc = "0x210 - L1-ICache0 Access Fail ID/attribution information register"]
921 #[inline(always)]
922 pub const fn l1_icache0_acs_fail_id_attr(&self) -> &L1_ICACHE0_ACS_FAIL_ID_ATTR {
923 &self.l1_icache0_acs_fail_id_attr
924 }
925 #[doc = "0x214 - L1-ICache0 Access Fail Address information register"]
926 #[inline(always)]
927 pub const fn l1_icache0_acs_fail_addr(&self) -> &L1_ICACHE0_ACS_FAIL_ADDR {
928 &self.l1_icache0_acs_fail_addr
929 }
930 #[doc = "0x218 - L1-ICache0 Access Fail ID/attribution information register"]
931 #[inline(always)]
932 pub const fn l1_icache1_acs_fail_id_attr(&self) -> &L1_ICACHE1_ACS_FAIL_ID_ATTR {
933 &self.l1_icache1_acs_fail_id_attr
934 }
935 #[doc = "0x21c - L1-ICache0 Access Fail Address information register"]
936 #[inline(always)]
937 pub const fn l1_icache1_acs_fail_addr(&self) -> &L1_ICACHE1_ACS_FAIL_ADDR {
938 &self.l1_icache1_acs_fail_addr
939 }
940 #[doc = "0x220 - L1-ICache0 Access Fail ID/attribution information register"]
941 #[inline(always)]
942 pub const fn l1_icache2_acs_fail_id_attr(&self) -> &L1_ICACHE2_ACS_FAIL_ID_ATTR {
943 &self.l1_icache2_acs_fail_id_attr
944 }
945 #[doc = "0x224 - L1-ICache0 Access Fail Address information register"]
946 #[inline(always)]
947 pub const fn l1_icache2_acs_fail_addr(&self) -> &L1_ICACHE2_ACS_FAIL_ADDR {
948 &self.l1_icache2_acs_fail_addr
949 }
950 #[doc = "0x228 - L1-ICache0 Access Fail ID/attribution information register"]
951 #[inline(always)]
952 pub const fn l1_icache3_acs_fail_id_attr(&self) -> &L1_ICACHE3_ACS_FAIL_ID_ATTR {
953 &self.l1_icache3_acs_fail_id_attr
954 }
955 #[doc = "0x22c - L1-ICache0 Access Fail Address information register"]
956 #[inline(always)]
957 pub const fn l1_icache3_acs_fail_addr(&self) -> &L1_ICACHE3_ACS_FAIL_ADDR {
958 &self.l1_icache3_acs_fail_addr
959 }
960 #[doc = "0x230 - L1-DCache Access Fail ID/attribution information register"]
961 #[inline(always)]
962 pub const fn l1_dcache_acs_fail_id_attr(&self) -> &L1_DCACHE_ACS_FAIL_ID_ATTR {
963 &self.l1_dcache_acs_fail_id_attr
964 }
965 #[doc = "0x234 - L1-DCache Access Fail Address information register"]
966 #[inline(always)]
967 pub const fn l1_dcache_acs_fail_addr(&self) -> &L1_DCACHE_ACS_FAIL_ADDR {
968 &self.l1_dcache_acs_fail_addr
969 }
970 #[doc = "0x238 - L1-Cache Access Fail Interrupt enable register"]
971 #[inline(always)]
972 pub const fn sync_l1_cache_preload_int_ena(&self) -> &SYNC_L1_CACHE_PRELOAD_INT_ENA {
973 &self.sync_l1_cache_preload_int_ena
974 }
975 #[doc = "0x23c - Sync Preload operation Interrupt clear register"]
976 #[inline(always)]
977 pub const fn sync_l1_cache_preload_int_clr(&self) -> &SYNC_L1_CACHE_PRELOAD_INT_CLR {
978 &self.sync_l1_cache_preload_int_clr
979 }
980 #[doc = "0x240 - Sync Preload operation Interrupt raw register"]
981 #[inline(always)]
982 pub const fn sync_l1_cache_preload_int_raw(&self) -> &SYNC_L1_CACHE_PRELOAD_INT_RAW {
983 &self.sync_l1_cache_preload_int_raw
984 }
985 #[doc = "0x244 - L1-Cache Access Fail Interrupt status register"]
986 #[inline(always)]
987 pub const fn sync_l1_cache_preload_int_st(&self) -> &SYNC_L1_CACHE_PRELOAD_INT_ST {
988 &self.sync_l1_cache_preload_int_st
989 }
990 #[doc = "0x248 - Cache Sync/Preload Operation exception register"]
991 #[inline(always)]
992 pub const fn sync_l1_cache_preload_exception(&self) -> &SYNC_L1_CACHE_PRELOAD_EXCEPTION {
993 &self.sync_l1_cache_preload_exception
994 }
995 #[doc = "0x24c - Cache Sync Reset control register"]
996 #[inline(always)]
997 pub const fn l1_cache_sync_rst_ctrl(&self) -> &L1_CACHE_SYNC_RST_CTRL {
998 &self.l1_cache_sync_rst_ctrl
999 }
1000 #[doc = "0x250 - Cache Preload Reset control register"]
1001 #[inline(always)]
1002 pub const fn l1_cache_preload_rst_ctrl(&self) -> &L1_CACHE_PRELOAD_RST_CTRL {
1003 &self.l1_cache_preload_rst_ctrl
1004 }
1005 #[doc = "0x254 - Cache Autoload buffer clear control register"]
1006 #[inline(always)]
1007 pub const fn l1_cache_autoload_buf_clr_ctrl(&self) -> &L1_CACHE_AUTOLOAD_BUF_CLR_CTRL {
1008 &self.l1_cache_autoload_buf_clr_ctrl
1009 }
1010 #[doc = "0x258 - Unallocate request buffer clear registers"]
1011 #[inline(always)]
1012 pub const fn l1_unallocate_buffer_clear(&self) -> &L1_UNALLOCATE_BUFFER_CLEAR {
1013 &self.l1_unallocate_buffer_clear
1014 }
1015 #[doc = "0x25c - Cache Tag and Data memory Object control register"]
1016 #[inline(always)]
1017 pub const fn l1_cache_object_ctrl(&self) -> &L1_CACHE_OBJECT_CTRL {
1018 &self.l1_cache_object_ctrl
1019 }
1020 #[doc = "0x260 - Cache Tag and Data memory way register"]
1021 #[inline(always)]
1022 pub const fn l1_cache_way_object(&self) -> &L1_CACHE_WAY_OBJECT {
1023 &self.l1_cache_way_object
1024 }
1025 #[doc = "0x264 - Cache Vaddr register"]
1026 #[inline(always)]
1027 pub const fn l1_cache_vaddr(&self) -> &L1_CACHE_VADDR {
1028 &self.l1_cache_vaddr
1029 }
1030 #[doc = "0x268 - Cache Tag/data memory content register"]
1031 #[inline(always)]
1032 pub const fn l1_cache_debug_bus(&self) -> &L1_CACHE_DEBUG_BUS {
1033 &self.l1_cache_debug_bus
1034 }
1035 #[doc = "0x26c - USED TO SPLIT L1 CACHE AND L2 CACHE"]
1036 #[inline(always)]
1037 pub const fn level_split0(&self) -> &LEVEL_SPLIT0 {
1038 &self.level_split0
1039 }
1040 #[doc = "0x270 - L2 Cache(L2-Cache) control register"]
1041 #[inline(always)]
1042 pub const fn l2_cache_ctrl(&self) -> &L2_CACHE_CTRL {
1043 &self.l2_cache_ctrl
1044 }
1045 #[doc = "0x274 - Bypass Cache configure register"]
1046 #[inline(always)]
1047 pub const fn l2_bypass_cache_conf(&self) -> &L2_BYPASS_CACHE_CONF {
1048 &self.l2_bypass_cache_conf
1049 }
1050 #[doc = "0x278 - L2 Cache CacheSize mode configure register"]
1051 #[inline(always)]
1052 pub const fn l2_cache_cachesize_conf(&self) -> &L2_CACHE_CACHESIZE_CONF {
1053 &self.l2_cache_cachesize_conf
1054 }
1055 #[doc = "0x27c - L2 Cache BlockSize mode configure register"]
1056 #[inline(always)]
1057 pub const fn l2_cache_blocksize_conf(&self) -> &L2_CACHE_BLOCKSIZE_CONF {
1058 &self.l2_cache_blocksize_conf
1059 }
1060 #[doc = "0x280 - Cache wrap around control register"]
1061 #[inline(always)]
1062 pub const fn l2_cache_wrap_around_ctrl(&self) -> &L2_CACHE_WRAP_AROUND_CTRL {
1063 &self.l2_cache_wrap_around_ctrl
1064 }
1065 #[doc = "0x284 - Cache tag memory power control register"]
1066 #[inline(always)]
1067 pub const fn l2_cache_tag_mem_power_ctrl(&self) -> &L2_CACHE_TAG_MEM_POWER_CTRL {
1068 &self.l2_cache_tag_mem_power_ctrl
1069 }
1070 #[doc = "0x288 - Cache data memory power control register"]
1071 #[inline(always)]
1072 pub const fn l2_cache_data_mem_power_ctrl(&self) -> &L2_CACHE_DATA_MEM_POWER_CTRL {
1073 &self.l2_cache_data_mem_power_ctrl
1074 }
1075 #[doc = "0x28c - Cache Freeze control register"]
1076 #[inline(always)]
1077 pub const fn l2_cache_freeze_ctrl(&self) -> &L2_CACHE_FREEZE_CTRL {
1078 &self.l2_cache_freeze_ctrl
1079 }
1080 #[doc = "0x290 - Cache data memory access configure register"]
1081 #[inline(always)]
1082 pub const fn l2_cache_data_mem_acs_conf(&self) -> &L2_CACHE_DATA_MEM_ACS_CONF {
1083 &self.l2_cache_data_mem_acs_conf
1084 }
1085 #[doc = "0x294 - Cache tag memory access configure register"]
1086 #[inline(always)]
1087 pub const fn l2_cache_tag_mem_acs_conf(&self) -> &L2_CACHE_TAG_MEM_ACS_CONF {
1088 &self.l2_cache_tag_mem_acs_conf
1089 }
1090 #[doc = "0x298 - L2 Cache prelock configure register"]
1091 #[inline(always)]
1092 pub const fn l2_cache_prelock_conf(&self) -> &L2_CACHE_PRELOCK_CONF {
1093 &self.l2_cache_prelock_conf
1094 }
1095 #[doc = "0x29c - L2 Cache prelock section0 address configure register"]
1096 #[inline(always)]
1097 pub const fn l2_cache_prelock_sct0_addr(&self) -> &L2_CACHE_PRELOCK_SCT0_ADDR {
1098 &self.l2_cache_prelock_sct0_addr
1099 }
1100 #[doc = "0x2a0 - L2 Cache prelock section1 address configure register"]
1101 #[inline(always)]
1102 pub const fn l2_cache_prelock_sct1_addr(&self) -> &L2_CACHE_PRELOCK_SCT1_ADDR {
1103 &self.l2_cache_prelock_sct1_addr
1104 }
1105 #[doc = "0x2a4 - L2 Cache prelock section size configure register"]
1106 #[inline(always)]
1107 pub const fn l2_cache_prelock_sct_size(&self) -> &L2_CACHE_PRELOCK_SCT_SIZE {
1108 &self.l2_cache_prelock_sct_size
1109 }
1110 #[doc = "0x2a8 - L2 Cache preload-operation control register"]
1111 #[inline(always)]
1112 pub const fn l2_cache_preload_ctrl(&self) -> &L2_CACHE_PRELOAD_CTRL {
1113 &self.l2_cache_preload_ctrl
1114 }
1115 #[doc = "0x2ac - L2 Cache preload address configure register"]
1116 #[inline(always)]
1117 pub const fn l2_cache_preload_addr(&self) -> &L2_CACHE_PRELOAD_ADDR {
1118 &self.l2_cache_preload_addr
1119 }
1120 #[doc = "0x2b0 - L2 Cache preload size configure register"]
1121 #[inline(always)]
1122 pub const fn l2_cache_preload_size(&self) -> &L2_CACHE_PRELOAD_SIZE {
1123 &self.l2_cache_preload_size
1124 }
1125 #[doc = "0x2b4 - L2 Cache autoload-operation control register"]
1126 #[inline(always)]
1127 pub const fn l2_cache_autoload_ctrl(&self) -> &L2_CACHE_AUTOLOAD_CTRL {
1128 &self.l2_cache_autoload_ctrl
1129 }
1130 #[doc = "0x2b8 - L2 Cache autoload section 0 address configure register"]
1131 #[inline(always)]
1132 pub const fn l2_cache_autoload_sct0_addr(&self) -> &L2_CACHE_AUTOLOAD_SCT0_ADDR {
1133 &self.l2_cache_autoload_sct0_addr
1134 }
1135 #[doc = "0x2bc - L2 Cache autoload section 0 size configure register"]
1136 #[inline(always)]
1137 pub const fn l2_cache_autoload_sct0_size(&self) -> &L2_CACHE_AUTOLOAD_SCT0_SIZE {
1138 &self.l2_cache_autoload_sct0_size
1139 }
1140 #[doc = "0x2c0 - L2 Cache autoload section 1 address configure register"]
1141 #[inline(always)]
1142 pub const fn l2_cache_autoload_sct1_addr(&self) -> &L2_CACHE_AUTOLOAD_SCT1_ADDR {
1143 &self.l2_cache_autoload_sct1_addr
1144 }
1145 #[doc = "0x2c4 - L2 Cache autoload section 1 size configure register"]
1146 #[inline(always)]
1147 pub const fn l2_cache_autoload_sct1_size(&self) -> &L2_CACHE_AUTOLOAD_SCT1_SIZE {
1148 &self.l2_cache_autoload_sct1_size
1149 }
1150 #[doc = "0x2c8 - L2 Cache autoload section 2 address configure register"]
1151 #[inline(always)]
1152 pub const fn l2_cache_autoload_sct2_addr(&self) -> &L2_CACHE_AUTOLOAD_SCT2_ADDR {
1153 &self.l2_cache_autoload_sct2_addr
1154 }
1155 #[doc = "0x2cc - L2 Cache autoload section 2 size configure register"]
1156 #[inline(always)]
1157 pub const fn l2_cache_autoload_sct2_size(&self) -> &L2_CACHE_AUTOLOAD_SCT2_SIZE {
1158 &self.l2_cache_autoload_sct2_size
1159 }
1160 #[doc = "0x2d0 - L2 Cache autoload section 3 address configure register"]
1161 #[inline(always)]
1162 pub const fn l2_cache_autoload_sct3_addr(&self) -> &L2_CACHE_AUTOLOAD_SCT3_ADDR {
1163 &self.l2_cache_autoload_sct3_addr
1164 }
1165 #[doc = "0x2d4 - L2 Cache autoload section 3 size configure register"]
1166 #[inline(always)]
1167 pub const fn l2_cache_autoload_sct3_size(&self) -> &L2_CACHE_AUTOLOAD_SCT3_SIZE {
1168 &self.l2_cache_autoload_sct3_size
1169 }
1170 #[doc = "0x2d8 - Cache Access Counter Interrupt enable register"]
1171 #[inline(always)]
1172 pub const fn l2_cache_acs_cnt_int_ena(&self) -> &L2_CACHE_ACS_CNT_INT_ENA {
1173 &self.l2_cache_acs_cnt_int_ena
1174 }
1175 #[doc = "0x2dc - Cache Access Counter Interrupt clear register"]
1176 #[inline(always)]
1177 pub const fn l2_cache_acs_cnt_int_clr(&self) -> &L2_CACHE_ACS_CNT_INT_CLR {
1178 &self.l2_cache_acs_cnt_int_clr
1179 }
1180 #[doc = "0x2e0 - Cache Access Counter Interrupt raw register"]
1181 #[inline(always)]
1182 pub const fn l2_cache_acs_cnt_int_raw(&self) -> &L2_CACHE_ACS_CNT_INT_RAW {
1183 &self.l2_cache_acs_cnt_int_raw
1184 }
1185 #[doc = "0x2e4 - Cache Access Counter Interrupt status register"]
1186 #[inline(always)]
1187 pub const fn l2_cache_acs_cnt_int_st(&self) -> &L2_CACHE_ACS_CNT_INT_ST {
1188 &self.l2_cache_acs_cnt_int_st
1189 }
1190 #[doc = "0x2e8 - Cache Access Fail Configuration register"]
1191 #[inline(always)]
1192 pub const fn l2_cache_acs_fail_ctrl(&self) -> &L2_CACHE_ACS_FAIL_CTRL {
1193 &self.l2_cache_acs_fail_ctrl
1194 }
1195 #[doc = "0x2ec - Cache Access Fail Interrupt enable register"]
1196 #[inline(always)]
1197 pub const fn l2_cache_acs_fail_int_ena(&self) -> &L2_CACHE_ACS_FAIL_INT_ENA {
1198 &self.l2_cache_acs_fail_int_ena
1199 }
1200 #[doc = "0x2f0 - L1-Cache Access Fail Interrupt clear register"]
1201 #[inline(always)]
1202 pub const fn l2_cache_acs_fail_int_clr(&self) -> &L2_CACHE_ACS_FAIL_INT_CLR {
1203 &self.l2_cache_acs_fail_int_clr
1204 }
1205 #[doc = "0x2f4 - Cache Access Fail Interrupt raw register"]
1206 #[inline(always)]
1207 pub const fn l2_cache_acs_fail_int_raw(&self) -> &L2_CACHE_ACS_FAIL_INT_RAW {
1208 &self.l2_cache_acs_fail_int_raw
1209 }
1210 #[doc = "0x2f8 - Cache Access Fail Interrupt status register"]
1211 #[inline(always)]
1212 pub const fn l2_cache_acs_fail_int_st(&self) -> &L2_CACHE_ACS_FAIL_INT_ST {
1213 &self.l2_cache_acs_fail_int_st
1214 }
1215 #[doc = "0x2fc - Cache Access Counter enable and clear register"]
1216 #[inline(always)]
1217 pub const fn l2_cache_acs_cnt_ctrl(&self) -> &L2_CACHE_ACS_CNT_CTRL {
1218 &self.l2_cache_acs_cnt_ctrl
1219 }
1220 #[doc = "0x300 - L2-Cache bus0 Hit-Access Counter register"]
1221 #[inline(always)]
1222 pub const fn l2_ibus0_acs_hit_cnt(&self) -> &L2_IBUS0_ACS_HIT_CNT {
1223 &self.l2_ibus0_acs_hit_cnt
1224 }
1225 #[doc = "0x304 - L2-Cache bus0 Miss-Access Counter register"]
1226 #[inline(always)]
1227 pub const fn l2_ibus0_acs_miss_cnt(&self) -> &L2_IBUS0_ACS_MISS_CNT {
1228 &self.l2_ibus0_acs_miss_cnt
1229 }
1230 #[doc = "0x308 - L2-Cache bus0 Conflict-Access Counter register"]
1231 #[inline(always)]
1232 pub const fn l2_ibus0_acs_conflict_cnt(&self) -> &L2_IBUS0_ACS_CONFLICT_CNT {
1233 &self.l2_ibus0_acs_conflict_cnt
1234 }
1235 #[doc = "0x30c - L2-Cache bus0 Next-Level-Access Counter register"]
1236 #[inline(always)]
1237 pub const fn l2_ibus0_acs_nxtlvl_rd_cnt(&self) -> &L2_IBUS0_ACS_NXTLVL_RD_CNT {
1238 &self.l2_ibus0_acs_nxtlvl_rd_cnt
1239 }
1240 #[doc = "0x310 - L2-Cache bus1 Hit-Access Counter register"]
1241 #[inline(always)]
1242 pub const fn l2_ibus1_acs_hit_cnt(&self) -> &L2_IBUS1_ACS_HIT_CNT {
1243 &self.l2_ibus1_acs_hit_cnt
1244 }
1245 #[doc = "0x314 - L2-Cache bus1 Miss-Access Counter register"]
1246 #[inline(always)]
1247 pub const fn l2_ibus1_acs_miss_cnt(&self) -> &L2_IBUS1_ACS_MISS_CNT {
1248 &self.l2_ibus1_acs_miss_cnt
1249 }
1250 #[doc = "0x318 - L2-Cache bus1 Conflict-Access Counter register"]
1251 #[inline(always)]
1252 pub const fn l2_ibus1_acs_conflict_cnt(&self) -> &L2_IBUS1_ACS_CONFLICT_CNT {
1253 &self.l2_ibus1_acs_conflict_cnt
1254 }
1255 #[doc = "0x31c - L2-Cache bus1 Next-Level-Access Counter register"]
1256 #[inline(always)]
1257 pub const fn l2_ibus1_acs_nxtlvl_rd_cnt(&self) -> &L2_IBUS1_ACS_NXTLVL_RD_CNT {
1258 &self.l2_ibus1_acs_nxtlvl_rd_cnt
1259 }
1260 #[doc = "0x320 - L2-Cache bus2 Hit-Access Counter register"]
1261 #[inline(always)]
1262 pub const fn l2_ibus2_acs_hit_cnt(&self) -> &L2_IBUS2_ACS_HIT_CNT {
1263 &self.l2_ibus2_acs_hit_cnt
1264 }
1265 #[doc = "0x324 - L2-Cache bus2 Miss-Access Counter register"]
1266 #[inline(always)]
1267 pub const fn l2_ibus2_acs_miss_cnt(&self) -> &L2_IBUS2_ACS_MISS_CNT {
1268 &self.l2_ibus2_acs_miss_cnt
1269 }
1270 #[doc = "0x328 - L2-Cache bus2 Conflict-Access Counter register"]
1271 #[inline(always)]
1272 pub const fn l2_ibus2_acs_conflict_cnt(&self) -> &L2_IBUS2_ACS_CONFLICT_CNT {
1273 &self.l2_ibus2_acs_conflict_cnt
1274 }
1275 #[doc = "0x32c - L2-Cache bus2 Next-Level-Access Counter register"]
1276 #[inline(always)]
1277 pub const fn l2_ibus2_acs_nxtlvl_rd_cnt(&self) -> &L2_IBUS2_ACS_NXTLVL_RD_CNT {
1278 &self.l2_ibus2_acs_nxtlvl_rd_cnt
1279 }
1280 #[doc = "0x330 - L2-Cache bus3 Hit-Access Counter register"]
1281 #[inline(always)]
1282 pub const fn l2_ibus3_acs_hit_cnt(&self) -> &L2_IBUS3_ACS_HIT_CNT {
1283 &self.l2_ibus3_acs_hit_cnt
1284 }
1285 #[doc = "0x334 - L2-Cache bus3 Miss-Access Counter register"]
1286 #[inline(always)]
1287 pub const fn l2_ibus3_acs_miss_cnt(&self) -> &L2_IBUS3_ACS_MISS_CNT {
1288 &self.l2_ibus3_acs_miss_cnt
1289 }
1290 #[doc = "0x338 - L2-Cache bus3 Conflict-Access Counter register"]
1291 #[inline(always)]
1292 pub const fn l2_ibus3_acs_conflict_cnt(&self) -> &L2_IBUS3_ACS_CONFLICT_CNT {
1293 &self.l2_ibus3_acs_conflict_cnt
1294 }
1295 #[doc = "0x33c - L2-Cache bus3 Next-Level-Access Counter register"]
1296 #[inline(always)]
1297 pub const fn l2_ibus3_acs_nxtlvl_rd_cnt(&self) -> &L2_IBUS3_ACS_NXTLVL_RD_CNT {
1298 &self.l2_ibus3_acs_nxtlvl_rd_cnt
1299 }
1300 #[doc = "0x340 - L2-Cache bus0 Hit-Access Counter register"]
1301 #[inline(always)]
1302 pub const fn l2_dbus0_acs_hit_cnt(&self) -> &L2_DBUS0_ACS_HIT_CNT {
1303 &self.l2_dbus0_acs_hit_cnt
1304 }
1305 #[doc = "0x344 - L2-Cache bus0 Miss-Access Counter register"]
1306 #[inline(always)]
1307 pub const fn l2_dbus0_acs_miss_cnt(&self) -> &L2_DBUS0_ACS_MISS_CNT {
1308 &self.l2_dbus0_acs_miss_cnt
1309 }
1310 #[doc = "0x348 - L2-Cache bus0 Conflict-Access Counter register"]
1311 #[inline(always)]
1312 pub const fn l2_dbus0_acs_conflict_cnt(&self) -> &L2_DBUS0_ACS_CONFLICT_CNT {
1313 &self.l2_dbus0_acs_conflict_cnt
1314 }
1315 #[doc = "0x34c - L2-Cache bus0 Next-Level-Access Counter register"]
1316 #[inline(always)]
1317 pub const fn l2_dbus0_acs_nxtlvl_rd_cnt(&self) -> &L2_DBUS0_ACS_NXTLVL_RD_CNT {
1318 &self.l2_dbus0_acs_nxtlvl_rd_cnt
1319 }
1320 #[doc = "0x350 - L2-Cache bus0 WB-Access Counter register"]
1321 #[inline(always)]
1322 pub const fn l2_dbus0_acs_nxtlvl_wr_cnt(&self) -> &L2_DBUS0_ACS_NXTLVL_WR_CNT {
1323 &self.l2_dbus0_acs_nxtlvl_wr_cnt
1324 }
1325 #[doc = "0x354 - L2-Cache bus1 Hit-Access Counter register"]
1326 #[inline(always)]
1327 pub const fn l2_dbus1_acs_hit_cnt(&self) -> &L2_DBUS1_ACS_HIT_CNT {
1328 &self.l2_dbus1_acs_hit_cnt
1329 }
1330 #[doc = "0x358 - L2-Cache bus1 Miss-Access Counter register"]
1331 #[inline(always)]
1332 pub const fn l2_dbus1_acs_miss_cnt(&self) -> &L2_DBUS1_ACS_MISS_CNT {
1333 &self.l2_dbus1_acs_miss_cnt
1334 }
1335 #[doc = "0x35c - L2-Cache bus1 Conflict-Access Counter register"]
1336 #[inline(always)]
1337 pub const fn l2_dbus1_acs_conflict_cnt(&self) -> &L2_DBUS1_ACS_CONFLICT_CNT {
1338 &self.l2_dbus1_acs_conflict_cnt
1339 }
1340 #[doc = "0x360 - L2-Cache bus1 Next-Level-Access Counter register"]
1341 #[inline(always)]
1342 pub const fn l2_dbus1_acs_nxtlvl_rd_cnt(&self) -> &L2_DBUS1_ACS_NXTLVL_RD_CNT {
1343 &self.l2_dbus1_acs_nxtlvl_rd_cnt
1344 }
1345 #[doc = "0x364 - L2-Cache bus1 WB-Access Counter register"]
1346 #[inline(always)]
1347 pub const fn l2_dbus1_acs_nxtlvl_wr_cnt(&self) -> &L2_DBUS1_ACS_NXTLVL_WR_CNT {
1348 &self.l2_dbus1_acs_nxtlvl_wr_cnt
1349 }
1350 #[doc = "0x368 - L2-Cache bus2 Hit-Access Counter register"]
1351 #[inline(always)]
1352 pub const fn l2_dbus2_acs_hit_cnt(&self) -> &L2_DBUS2_ACS_HIT_CNT {
1353 &self.l2_dbus2_acs_hit_cnt
1354 }
1355 #[doc = "0x36c - L2-Cache bus2 Miss-Access Counter register"]
1356 #[inline(always)]
1357 pub const fn l2_dbus2_acs_miss_cnt(&self) -> &L2_DBUS2_ACS_MISS_CNT {
1358 &self.l2_dbus2_acs_miss_cnt
1359 }
1360 #[doc = "0x370 - L2-Cache bus2 Conflict-Access Counter register"]
1361 #[inline(always)]
1362 pub const fn l2_dbus2_acs_conflict_cnt(&self) -> &L2_DBUS2_ACS_CONFLICT_CNT {
1363 &self.l2_dbus2_acs_conflict_cnt
1364 }
1365 #[doc = "0x374 - L2-Cache bus2 Next-Level-Access Counter register"]
1366 #[inline(always)]
1367 pub const fn l2_dbus2_acs_nxtlvl_rd_cnt(&self) -> &L2_DBUS2_ACS_NXTLVL_RD_CNT {
1368 &self.l2_dbus2_acs_nxtlvl_rd_cnt
1369 }
1370 #[doc = "0x378 - L2-Cache bus2 WB-Access Counter register"]
1371 #[inline(always)]
1372 pub const fn l2_dbus2_acs_nxtlvl_wr_cnt(&self) -> &L2_DBUS2_ACS_NXTLVL_WR_CNT {
1373 &self.l2_dbus2_acs_nxtlvl_wr_cnt
1374 }
1375 #[doc = "0x37c - L2-Cache bus3 Hit-Access Counter register"]
1376 #[inline(always)]
1377 pub const fn l2_dbus3_acs_hit_cnt(&self) -> &L2_DBUS3_ACS_HIT_CNT {
1378 &self.l2_dbus3_acs_hit_cnt
1379 }
1380 #[doc = "0x380 - L2-Cache bus3 Miss-Access Counter register"]
1381 #[inline(always)]
1382 pub const fn l2_dbus3_acs_miss_cnt(&self) -> &L2_DBUS3_ACS_MISS_CNT {
1383 &self.l2_dbus3_acs_miss_cnt
1384 }
1385 #[doc = "0x384 - L2-Cache bus3 Conflict-Access Counter register"]
1386 #[inline(always)]
1387 pub const fn l2_dbus3_acs_conflict_cnt(&self) -> &L2_DBUS3_ACS_CONFLICT_CNT {
1388 &self.l2_dbus3_acs_conflict_cnt
1389 }
1390 #[doc = "0x388 - L2-Cache bus3 Next-Level-Access Counter register"]
1391 #[inline(always)]
1392 pub const fn l2_dbus3_acs_nxtlvl_rd_cnt(&self) -> &L2_DBUS3_ACS_NXTLVL_RD_CNT {
1393 &self.l2_dbus3_acs_nxtlvl_rd_cnt
1394 }
1395 #[doc = "0x38c - L2-Cache bus3 WB-Access Counter register"]
1396 #[inline(always)]
1397 pub const fn l2_dbus3_acs_nxtlvl_wr_cnt(&self) -> &L2_DBUS3_ACS_NXTLVL_WR_CNT {
1398 &self.l2_dbus3_acs_nxtlvl_wr_cnt
1399 }
1400 #[doc = "0x390 - L2-Cache Access Fail ID/attribution information register"]
1401 #[inline(always)]
1402 pub const fn l2_cache_acs_fail_id_attr(&self) -> &L2_CACHE_ACS_FAIL_ID_ATTR {
1403 &self.l2_cache_acs_fail_id_attr
1404 }
1405 #[doc = "0x394 - L2-Cache Access Fail Address information register"]
1406 #[inline(always)]
1407 pub const fn l2_cache_acs_fail_addr(&self) -> &L2_CACHE_ACS_FAIL_ADDR {
1408 &self.l2_cache_acs_fail_addr
1409 }
1410 #[doc = "0x398 - L1-Cache Access Fail Interrupt enable register"]
1411 #[inline(always)]
1412 pub const fn l2_cache_sync_preload_int_ena(&self) -> &L2_CACHE_SYNC_PRELOAD_INT_ENA {
1413 &self.l2_cache_sync_preload_int_ena
1414 }
1415 #[doc = "0x39c - Sync Preload operation Interrupt clear register"]
1416 #[inline(always)]
1417 pub const fn l2_cache_sync_preload_int_clr(&self) -> &L2_CACHE_SYNC_PRELOAD_INT_CLR {
1418 &self.l2_cache_sync_preload_int_clr
1419 }
1420 #[doc = "0x3a0 - Sync Preload operation Interrupt raw register"]
1421 #[inline(always)]
1422 pub const fn l2_cache_sync_preload_int_raw(&self) -> &L2_CACHE_SYNC_PRELOAD_INT_RAW {
1423 &self.l2_cache_sync_preload_int_raw
1424 }
1425 #[doc = "0x3a4 - L1-Cache Access Fail Interrupt status register"]
1426 #[inline(always)]
1427 pub const fn l2_cache_sync_preload_int_st(&self) -> &L2_CACHE_SYNC_PRELOAD_INT_ST {
1428 &self.l2_cache_sync_preload_int_st
1429 }
1430 #[doc = "0x3a8 - Cache Sync/Preload Operation exception register"]
1431 #[inline(always)]
1432 pub const fn l2_cache_sync_preload_exception(&self) -> &L2_CACHE_SYNC_PRELOAD_EXCEPTION {
1433 &self.l2_cache_sync_preload_exception
1434 }
1435 #[doc = "0x3ac - Cache Sync Reset control register"]
1436 #[inline(always)]
1437 pub const fn l2_cache_sync_rst_ctrl(&self) -> &L2_CACHE_SYNC_RST_CTRL {
1438 &self.l2_cache_sync_rst_ctrl
1439 }
1440 #[doc = "0x3b0 - Cache Preload Reset control register"]
1441 #[inline(always)]
1442 pub const fn l2_cache_preload_rst_ctrl(&self) -> &L2_CACHE_PRELOAD_RST_CTRL {
1443 &self.l2_cache_preload_rst_ctrl
1444 }
1445 #[doc = "0x3b4 - Cache Autoload buffer clear control register"]
1446 #[inline(always)]
1447 pub const fn l2_cache_autoload_buf_clr_ctrl(&self) -> &L2_CACHE_AUTOLOAD_BUF_CLR_CTRL {
1448 &self.l2_cache_autoload_buf_clr_ctrl
1449 }
1450 #[doc = "0x3b8 - Unallocate request buffer clear registers"]
1451 #[inline(always)]
1452 pub const fn l2_unallocate_buffer_clear(&self) -> &L2_UNALLOCATE_BUFFER_CLEAR {
1453 &self.l2_unallocate_buffer_clear
1454 }
1455 #[doc = "0x3bc - L2 cache access attribute control register"]
1456 #[inline(always)]
1457 pub const fn l2_cache_access_attr_ctrl(&self) -> &L2_CACHE_ACCESS_ATTR_CTRL {
1458 &self.l2_cache_access_attr_ctrl
1459 }
1460 #[doc = "0x3c0 - Cache Tag and Data memory Object control register"]
1461 #[inline(always)]
1462 pub const fn l2_cache_object_ctrl(&self) -> &L2_CACHE_OBJECT_CTRL {
1463 &self.l2_cache_object_ctrl
1464 }
1465 #[doc = "0x3c4 - Cache Tag and Data memory way register"]
1466 #[inline(always)]
1467 pub const fn l2_cache_way_object(&self) -> &L2_CACHE_WAY_OBJECT {
1468 &self.l2_cache_way_object
1469 }
1470 #[doc = "0x3c8 - Cache Vaddr register"]
1471 #[inline(always)]
1472 pub const fn l2_cache_vaddr(&self) -> &L2_CACHE_VADDR {
1473 &self.l2_cache_vaddr
1474 }
1475 #[doc = "0x3cc - Cache Tag/data memory content register"]
1476 #[inline(always)]
1477 pub const fn l2_cache_debug_bus(&self) -> &L2_CACHE_DEBUG_BUS {
1478 &self.l2_cache_debug_bus
1479 }
1480 #[doc = "0x3d0 - USED TO SPLIT L1 CACHE AND L2 CACHE"]
1481 #[inline(always)]
1482 pub const fn level_split1(&self) -> &LEVEL_SPLIT1 {
1483 &self.level_split1
1484 }
1485 #[doc = "0x3d4 - Clock gate control register"]
1486 #[inline(always)]
1487 pub const fn clock_gate(&self) -> &CLOCK_GATE {
1488 &self.clock_gate
1489 }
1490 #[doc = "0x3d8 - Cache redundancy signal 0 register"]
1491 #[inline(always)]
1492 pub const fn redundancy_sig0(&self) -> &REDUNDANCY_SIG0 {
1493 &self.redundancy_sig0
1494 }
1495 #[doc = "0x3dc - Cache redundancy signal 1 register"]
1496 #[inline(always)]
1497 pub const fn redundancy_sig1(&self) -> &REDUNDANCY_SIG1 {
1498 &self.redundancy_sig1
1499 }
1500 #[doc = "0x3e0 - Cache redundancy signal 2 register"]
1501 #[inline(always)]
1502 pub const fn redundancy_sig2(&self) -> &REDUNDANCY_SIG2 {
1503 &self.redundancy_sig2
1504 }
1505 #[doc = "0x3e4 - Cache redundancy signal 3 register"]
1506 #[inline(always)]
1507 pub const fn redundancy_sig3(&self) -> &REDUNDANCY_SIG3 {
1508 &self.redundancy_sig3
1509 }
1510 #[doc = "0x3e8 - Cache redundancy signal 0 register"]
1511 #[inline(always)]
1512 pub const fn redundancy_sig4(&self) -> &REDUNDANCY_SIG4 {
1513 &self.redundancy_sig4
1514 }
1515 #[doc = "0x3fc - Version control register"]
1516 #[inline(always)]
1517 pub const fn date(&self) -> &DATE {
1518 &self.date
1519 }
1520}
1521#[doc = "L1_ICACHE_CTRL (rw) register accessor: L1 instruction Cache(L1-ICache) control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache_ctrl`] module"]
1522pub type L1_ICACHE_CTRL = crate::Reg<l1_icache_ctrl::L1_ICACHE_CTRL_SPEC>;
1523#[doc = "L1 instruction Cache(L1-ICache) control register"]
1524pub mod l1_icache_ctrl;
1525#[doc = "L1_DCACHE_CTRL (rw) register accessor: L1 data Cache(L1-DCache) control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_ctrl`] module"]
1526pub type L1_DCACHE_CTRL = crate::Reg<l1_dcache_ctrl::L1_DCACHE_CTRL_SPEC>;
1527#[doc = "L1 data Cache(L1-DCache) control register"]
1528pub mod l1_dcache_ctrl;
1529#[doc = "L1_BYPASS_CACHE_CONF (rw) register accessor: Bypass Cache configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_bypass_cache_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_bypass_cache_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_bypass_cache_conf`] module"]
1530pub type L1_BYPASS_CACHE_CONF = crate::Reg<l1_bypass_cache_conf::L1_BYPASS_CACHE_CONF_SPEC>;
1531#[doc = "Bypass Cache configure register"]
1532pub mod l1_bypass_cache_conf;
1533#[doc = "L1_CACHE_ATOMIC_CONF (rw) register accessor: L1 Cache atomic feature configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_atomic_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_atomic_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_atomic_conf`] module"]
1534pub type L1_CACHE_ATOMIC_CONF = crate::Reg<l1_cache_atomic_conf::L1_CACHE_ATOMIC_CONF_SPEC>;
1535#[doc = "L1 Cache atomic feature configure register"]
1536pub mod l1_cache_atomic_conf;
1537#[doc = "L1_ICACHE_CACHESIZE_CONF (r) register accessor: L1 instruction Cache CacheSize mode configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache_cachesize_conf::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache_cachesize_conf`] module"]
1538pub type L1_ICACHE_CACHESIZE_CONF =
1539 crate::Reg<l1_icache_cachesize_conf::L1_ICACHE_CACHESIZE_CONF_SPEC>;
1540#[doc = "L1 instruction Cache CacheSize mode configure register"]
1541pub mod l1_icache_cachesize_conf;
1542#[doc = "L1_ICACHE_BLOCKSIZE_CONF (r) register accessor: L1 instruction Cache BlockSize mode configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache_blocksize_conf::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache_blocksize_conf`] module"]
1543pub type L1_ICACHE_BLOCKSIZE_CONF =
1544 crate::Reg<l1_icache_blocksize_conf::L1_ICACHE_BLOCKSIZE_CONF_SPEC>;
1545#[doc = "L1 instruction Cache BlockSize mode configure register"]
1546pub mod l1_icache_blocksize_conf;
1547#[doc = "L1_DCACHE_CACHESIZE_CONF (r) register accessor: L1 data Cache CacheSize mode configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_cachesize_conf::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_cachesize_conf`] module"]
1548pub type L1_DCACHE_CACHESIZE_CONF =
1549 crate::Reg<l1_dcache_cachesize_conf::L1_DCACHE_CACHESIZE_CONF_SPEC>;
1550#[doc = "L1 data Cache CacheSize mode configure register"]
1551pub mod l1_dcache_cachesize_conf;
1552#[doc = "L1_DCACHE_BLOCKSIZE_CONF (r) register accessor: L1 data Cache BlockSize mode configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_blocksize_conf::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_blocksize_conf`] module"]
1553pub type L1_DCACHE_BLOCKSIZE_CONF =
1554 crate::Reg<l1_dcache_blocksize_conf::L1_DCACHE_BLOCKSIZE_CONF_SPEC>;
1555#[doc = "L1 data Cache BlockSize mode configure register"]
1556pub mod l1_dcache_blocksize_conf;
1557#[doc = "L1_CACHE_WRAP_AROUND_CTRL (rw) register accessor: Cache wrap around control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_wrap_around_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_wrap_around_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_wrap_around_ctrl`] module"]
1558pub type L1_CACHE_WRAP_AROUND_CTRL =
1559 crate::Reg<l1_cache_wrap_around_ctrl::L1_CACHE_WRAP_AROUND_CTRL_SPEC>;
1560#[doc = "Cache wrap around control register"]
1561pub mod l1_cache_wrap_around_ctrl;
1562#[doc = "L1_CACHE_TAG_MEM_POWER_CTRL (rw) register accessor: Cache tag memory power control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_tag_mem_power_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_tag_mem_power_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_tag_mem_power_ctrl`] module"]
1563pub type L1_CACHE_TAG_MEM_POWER_CTRL =
1564 crate::Reg<l1_cache_tag_mem_power_ctrl::L1_CACHE_TAG_MEM_POWER_CTRL_SPEC>;
1565#[doc = "Cache tag memory power control register"]
1566pub mod l1_cache_tag_mem_power_ctrl;
1567#[doc = "L1_CACHE_DATA_MEM_POWER_CTRL (rw) register accessor: Cache data memory power control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_data_mem_power_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_data_mem_power_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_data_mem_power_ctrl`] module"]
1568pub type L1_CACHE_DATA_MEM_POWER_CTRL =
1569 crate::Reg<l1_cache_data_mem_power_ctrl::L1_CACHE_DATA_MEM_POWER_CTRL_SPEC>;
1570#[doc = "Cache data memory power control register"]
1571pub mod l1_cache_data_mem_power_ctrl;
1572#[doc = "L1_CACHE_FREEZE_CTRL (rw) register accessor: Cache Freeze control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_freeze_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_freeze_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_freeze_ctrl`] module"]
1573pub type L1_CACHE_FREEZE_CTRL = crate::Reg<l1_cache_freeze_ctrl::L1_CACHE_FREEZE_CTRL_SPEC>;
1574#[doc = "Cache Freeze control register"]
1575pub mod l1_cache_freeze_ctrl;
1576#[doc = "L1_CACHE_DATA_MEM_ACS_CONF (rw) register accessor: Cache data memory access configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_data_mem_acs_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_data_mem_acs_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_data_mem_acs_conf`] module"]
1577pub type L1_CACHE_DATA_MEM_ACS_CONF =
1578 crate::Reg<l1_cache_data_mem_acs_conf::L1_CACHE_DATA_MEM_ACS_CONF_SPEC>;
1579#[doc = "Cache data memory access configure register"]
1580pub mod l1_cache_data_mem_acs_conf;
1581#[doc = "L1_CACHE_TAG_MEM_ACS_CONF (rw) register accessor: Cache tag memory access configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_tag_mem_acs_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_tag_mem_acs_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_tag_mem_acs_conf`] module"]
1582pub type L1_CACHE_TAG_MEM_ACS_CONF =
1583 crate::Reg<l1_cache_tag_mem_acs_conf::L1_CACHE_TAG_MEM_ACS_CONF_SPEC>;
1584#[doc = "Cache tag memory access configure register"]
1585pub mod l1_cache_tag_mem_acs_conf;
1586#[doc = "L1_ICACHE0_PRELOCK_CONF (rw) register accessor: L1 instruction Cache 0 prelock configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_prelock_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_prelock_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache0_prelock_conf`] module"]
1587pub type L1_ICACHE0_PRELOCK_CONF =
1588 crate::Reg<l1_icache0_prelock_conf::L1_ICACHE0_PRELOCK_CONF_SPEC>;
1589#[doc = "L1 instruction Cache 0 prelock configure register"]
1590pub mod l1_icache0_prelock_conf;
1591#[doc = "L1_ICACHE0_PRELOCK_SCT0_ADDR (rw) register accessor: L1 instruction Cache 0 prelock section0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_prelock_sct0_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_prelock_sct0_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache0_prelock_sct0_addr`] module"]
1592pub type L1_ICACHE0_PRELOCK_SCT0_ADDR =
1593 crate::Reg<l1_icache0_prelock_sct0_addr::L1_ICACHE0_PRELOCK_SCT0_ADDR_SPEC>;
1594#[doc = "L1 instruction Cache 0 prelock section0 address configure register"]
1595pub mod l1_icache0_prelock_sct0_addr;
1596#[doc = "L1_ICACHE0_PRELOCK_SCT1_ADDR (rw) register accessor: L1 instruction Cache 0 prelock section1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_prelock_sct1_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_prelock_sct1_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache0_prelock_sct1_addr`] module"]
1597pub type L1_ICACHE0_PRELOCK_SCT1_ADDR =
1598 crate::Reg<l1_icache0_prelock_sct1_addr::L1_ICACHE0_PRELOCK_SCT1_ADDR_SPEC>;
1599#[doc = "L1 instruction Cache 0 prelock section1 address configure register"]
1600pub mod l1_icache0_prelock_sct1_addr;
1601#[doc = "L1_ICACHE0_PRELOCK_SCT_SIZE (rw) register accessor: L1 instruction Cache 0 prelock section size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_prelock_sct_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_prelock_sct_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache0_prelock_sct_size`] module"]
1602pub type L1_ICACHE0_PRELOCK_SCT_SIZE =
1603 crate::Reg<l1_icache0_prelock_sct_size::L1_ICACHE0_PRELOCK_SCT_SIZE_SPEC>;
1604#[doc = "L1 instruction Cache 0 prelock section size configure register"]
1605pub mod l1_icache0_prelock_sct_size;
1606#[doc = "L1_ICACHE1_PRELOCK_CONF (rw) register accessor: L1 instruction Cache 1 prelock configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_prelock_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_prelock_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache1_prelock_conf`] module"]
1607pub type L1_ICACHE1_PRELOCK_CONF =
1608 crate::Reg<l1_icache1_prelock_conf::L1_ICACHE1_PRELOCK_CONF_SPEC>;
1609#[doc = "L1 instruction Cache 1 prelock configure register"]
1610pub mod l1_icache1_prelock_conf;
1611#[doc = "L1_ICACHE1_PRELOCK_SCT0_ADDR (rw) register accessor: L1 instruction Cache 1 prelock section0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_prelock_sct0_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_prelock_sct0_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache1_prelock_sct0_addr`] module"]
1612pub type L1_ICACHE1_PRELOCK_SCT0_ADDR =
1613 crate::Reg<l1_icache1_prelock_sct0_addr::L1_ICACHE1_PRELOCK_SCT0_ADDR_SPEC>;
1614#[doc = "L1 instruction Cache 1 prelock section0 address configure register"]
1615pub mod l1_icache1_prelock_sct0_addr;
1616#[doc = "L1_ICACHE1_PRELOCK_SCT1_ADDR (rw) register accessor: L1 instruction Cache 1 prelock section1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_prelock_sct1_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_prelock_sct1_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache1_prelock_sct1_addr`] module"]
1617pub type L1_ICACHE1_PRELOCK_SCT1_ADDR =
1618 crate::Reg<l1_icache1_prelock_sct1_addr::L1_ICACHE1_PRELOCK_SCT1_ADDR_SPEC>;
1619#[doc = "L1 instruction Cache 1 prelock section1 address configure register"]
1620pub mod l1_icache1_prelock_sct1_addr;
1621#[doc = "L1_ICACHE1_PRELOCK_SCT_SIZE (rw) register accessor: L1 instruction Cache 1 prelock section size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_prelock_sct_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_prelock_sct_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache1_prelock_sct_size`] module"]
1622pub type L1_ICACHE1_PRELOCK_SCT_SIZE =
1623 crate::Reg<l1_icache1_prelock_sct_size::L1_ICACHE1_PRELOCK_SCT_SIZE_SPEC>;
1624#[doc = "L1 instruction Cache 1 prelock section size configure register"]
1625pub mod l1_icache1_prelock_sct_size;
1626#[doc = "L1_ICACHE2_PRELOCK_CONF (r) register accessor: L1 instruction Cache 2 prelock configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_prelock_conf::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache2_prelock_conf`] module"]
1627pub type L1_ICACHE2_PRELOCK_CONF =
1628 crate::Reg<l1_icache2_prelock_conf::L1_ICACHE2_PRELOCK_CONF_SPEC>;
1629#[doc = "L1 instruction Cache 2 prelock configure register"]
1630pub mod l1_icache2_prelock_conf;
1631#[doc = "L1_ICACHE2_PRELOCK_SCT0_ADDR (r) register accessor: L1 instruction Cache 2 prelock section0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_prelock_sct0_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache2_prelock_sct0_addr`] module"]
1632pub type L1_ICACHE2_PRELOCK_SCT0_ADDR =
1633 crate::Reg<l1_icache2_prelock_sct0_addr::L1_ICACHE2_PRELOCK_SCT0_ADDR_SPEC>;
1634#[doc = "L1 instruction Cache 2 prelock section0 address configure register"]
1635pub mod l1_icache2_prelock_sct0_addr;
1636#[doc = "L1_ICACHE2_PRELOCK_SCT1_ADDR (r) register accessor: L1 instruction Cache 2 prelock section1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_prelock_sct1_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache2_prelock_sct1_addr`] module"]
1637pub type L1_ICACHE2_PRELOCK_SCT1_ADDR =
1638 crate::Reg<l1_icache2_prelock_sct1_addr::L1_ICACHE2_PRELOCK_SCT1_ADDR_SPEC>;
1639#[doc = "L1 instruction Cache 2 prelock section1 address configure register"]
1640pub mod l1_icache2_prelock_sct1_addr;
1641#[doc = "L1_ICACHE2_PRELOCK_SCT_SIZE (r) register accessor: L1 instruction Cache 2 prelock section size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_prelock_sct_size::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache2_prelock_sct_size`] module"]
1642pub type L1_ICACHE2_PRELOCK_SCT_SIZE =
1643 crate::Reg<l1_icache2_prelock_sct_size::L1_ICACHE2_PRELOCK_SCT_SIZE_SPEC>;
1644#[doc = "L1 instruction Cache 2 prelock section size configure register"]
1645pub mod l1_icache2_prelock_sct_size;
1646#[doc = "L1_ICACHE3_PRELOCK_CONF (r) register accessor: L1 instruction Cache 3 prelock configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_prelock_conf::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache3_prelock_conf`] module"]
1647pub type L1_ICACHE3_PRELOCK_CONF =
1648 crate::Reg<l1_icache3_prelock_conf::L1_ICACHE3_PRELOCK_CONF_SPEC>;
1649#[doc = "L1 instruction Cache 3 prelock configure register"]
1650pub mod l1_icache3_prelock_conf;
1651#[doc = "L1_ICACHE3_PRELOCK_SCT0_ADDR (r) register accessor: L1 instruction Cache 3 prelock section0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_prelock_sct0_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache3_prelock_sct0_addr`] module"]
1652pub type L1_ICACHE3_PRELOCK_SCT0_ADDR =
1653 crate::Reg<l1_icache3_prelock_sct0_addr::L1_ICACHE3_PRELOCK_SCT0_ADDR_SPEC>;
1654#[doc = "L1 instruction Cache 3 prelock section0 address configure register"]
1655pub mod l1_icache3_prelock_sct0_addr;
1656#[doc = "L1_ICACHE3_PRELOCK_SCT1_ADDR (r) register accessor: L1 instruction Cache 3 prelock section1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_prelock_sct1_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache3_prelock_sct1_addr`] module"]
1657pub type L1_ICACHE3_PRELOCK_SCT1_ADDR =
1658 crate::Reg<l1_icache3_prelock_sct1_addr::L1_ICACHE3_PRELOCK_SCT1_ADDR_SPEC>;
1659#[doc = "L1 instruction Cache 3 prelock section1 address configure register"]
1660pub mod l1_icache3_prelock_sct1_addr;
1661#[doc = "L1_ICACHE3_PRELOCK_SCT_SIZE (r) register accessor: L1 instruction Cache 3 prelock section size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_prelock_sct_size::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache3_prelock_sct_size`] module"]
1662pub type L1_ICACHE3_PRELOCK_SCT_SIZE =
1663 crate::Reg<l1_icache3_prelock_sct_size::L1_ICACHE3_PRELOCK_SCT_SIZE_SPEC>;
1664#[doc = "L1 instruction Cache 3 prelock section size configure register"]
1665pub mod l1_icache3_prelock_sct_size;
1666#[doc = "L1_DCACHE_PRELOCK_CONF (rw) register accessor: L1 data Cache prelock configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_prelock_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_prelock_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_prelock_conf`] module"]
1667pub type L1_DCACHE_PRELOCK_CONF = crate::Reg<l1_dcache_prelock_conf::L1_DCACHE_PRELOCK_CONF_SPEC>;
1668#[doc = "L1 data Cache prelock configure register"]
1669pub mod l1_dcache_prelock_conf;
1670#[doc = "L1_DCACHE_PRELOCK_SCT0_ADDR (rw) register accessor: L1 data Cache prelock section0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_prelock_sct0_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_prelock_sct0_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_prelock_sct0_addr`] module"]
1671pub type L1_DCACHE_PRELOCK_SCT0_ADDR =
1672 crate::Reg<l1_dcache_prelock_sct0_addr::L1_DCACHE_PRELOCK_SCT0_ADDR_SPEC>;
1673#[doc = "L1 data Cache prelock section0 address configure register"]
1674pub mod l1_dcache_prelock_sct0_addr;
1675#[doc = "L1_DCACHE_PRELOCK_SCT1_ADDR (rw) register accessor: L1 data Cache prelock section1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_prelock_sct1_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_prelock_sct1_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_prelock_sct1_addr`] module"]
1676pub type L1_DCACHE_PRELOCK_SCT1_ADDR =
1677 crate::Reg<l1_dcache_prelock_sct1_addr::L1_DCACHE_PRELOCK_SCT1_ADDR_SPEC>;
1678#[doc = "L1 data Cache prelock section1 address configure register"]
1679pub mod l1_dcache_prelock_sct1_addr;
1680#[doc = "L1_DCACHE_PRELOCK_SCT_SIZE (rw) register accessor: L1 data Cache prelock section size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_prelock_sct_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_prelock_sct_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_prelock_sct_size`] module"]
1681pub type L1_DCACHE_PRELOCK_SCT_SIZE =
1682 crate::Reg<l1_dcache_prelock_sct_size::L1_DCACHE_PRELOCK_SCT_SIZE_SPEC>;
1683#[doc = "L1 data Cache prelock section size configure register"]
1684pub mod l1_dcache_prelock_sct_size;
1685#[doc = "LOCK_CTRL (rw) register accessor: Lock-class (manual lock) operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lock_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lock_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lock_ctrl`] module"]
1686pub type LOCK_CTRL = crate::Reg<lock_ctrl::LOCK_CTRL_SPEC>;
1687#[doc = "Lock-class (manual lock) operation control register"]
1688pub mod lock_ctrl;
1689#[doc = "LOCK_MAP (rw) register accessor: Lock (manual lock) map configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lock_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lock_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lock_map`] module"]
1690pub type LOCK_MAP = crate::Reg<lock_map::LOCK_MAP_SPEC>;
1691#[doc = "Lock (manual lock) map configure register"]
1692pub mod lock_map;
1693#[doc = "LOCK_ADDR (rw) register accessor: Lock (manual lock) address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lock_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lock_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lock_addr`] module"]
1694pub type LOCK_ADDR = crate::Reg<lock_addr::LOCK_ADDR_SPEC>;
1695#[doc = "Lock (manual lock) address configure register"]
1696pub mod lock_addr;
1697#[doc = "LOCK_SIZE (rw) register accessor: Lock (manual lock) size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lock_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lock_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lock_size`] module"]
1698pub type LOCK_SIZE = crate::Reg<lock_size::LOCK_SIZE_SPEC>;
1699#[doc = "Lock (manual lock) size configure register"]
1700pub mod lock_size;
1701#[doc = "SYNC_CTRL (rw) register accessor: Sync-class operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sync_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sync_ctrl`] module"]
1702pub type SYNC_CTRL = crate::Reg<sync_ctrl::SYNC_CTRL_SPEC>;
1703#[doc = "Sync-class operation control register"]
1704pub mod sync_ctrl;
1705#[doc = "SYNC_MAP (rw) register accessor: Sync map configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sync_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sync_map`] module"]
1706pub type SYNC_MAP = crate::Reg<sync_map::SYNC_MAP_SPEC>;
1707#[doc = "Sync map configure register"]
1708pub mod sync_map;
1709#[doc = "SYNC_ADDR (rw) register accessor: Sync address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sync_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sync_addr`] module"]
1710pub type SYNC_ADDR = crate::Reg<sync_addr::SYNC_ADDR_SPEC>;
1711#[doc = "Sync address configure register"]
1712pub mod sync_addr;
1713#[doc = "SYNC_SIZE (rw) register accessor: Sync size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sync_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sync_size`] module"]
1714pub type SYNC_SIZE = crate::Reg<sync_size::SYNC_SIZE_SPEC>;
1715#[doc = "Sync size configure register"]
1716pub mod sync_size;
1717#[doc = "L1_ICACHE0_PRELOAD_CTRL (rw) register accessor: L1 instruction Cache 0 preload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_preload_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_preload_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache0_preload_ctrl`] module"]
1718pub type L1_ICACHE0_PRELOAD_CTRL =
1719 crate::Reg<l1_icache0_preload_ctrl::L1_ICACHE0_PRELOAD_CTRL_SPEC>;
1720#[doc = "L1 instruction Cache 0 preload-operation control register"]
1721pub mod l1_icache0_preload_ctrl;
1722#[doc = "L1_ICACHE0_PRELOAD_ADDR (rw) register accessor: L1 instruction Cache 0 preload address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_preload_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_preload_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache0_preload_addr`] module"]
1723pub type L1_ICACHE0_PRELOAD_ADDR =
1724 crate::Reg<l1_icache0_preload_addr::L1_ICACHE0_PRELOAD_ADDR_SPEC>;
1725#[doc = "L1 instruction Cache 0 preload address configure register"]
1726pub mod l1_icache0_preload_addr;
1727#[doc = "L1_ICACHE0_PRELOAD_SIZE (rw) register accessor: L1 instruction Cache 0 preload size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_preload_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_preload_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache0_preload_size`] module"]
1728pub type L1_ICACHE0_PRELOAD_SIZE =
1729 crate::Reg<l1_icache0_preload_size::L1_ICACHE0_PRELOAD_SIZE_SPEC>;
1730#[doc = "L1 instruction Cache 0 preload size configure register"]
1731pub mod l1_icache0_preload_size;
1732#[doc = "L1_ICACHE1_PRELOAD_CTRL (rw) register accessor: L1 instruction Cache 1 preload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_preload_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_preload_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache1_preload_ctrl`] module"]
1733pub type L1_ICACHE1_PRELOAD_CTRL =
1734 crate::Reg<l1_icache1_preload_ctrl::L1_ICACHE1_PRELOAD_CTRL_SPEC>;
1735#[doc = "L1 instruction Cache 1 preload-operation control register"]
1736pub mod l1_icache1_preload_ctrl;
1737#[doc = "L1_ICACHE1_PRELOAD_ADDR (rw) register accessor: L1 instruction Cache 1 preload address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_preload_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_preload_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache1_preload_addr`] module"]
1738pub type L1_ICACHE1_PRELOAD_ADDR =
1739 crate::Reg<l1_icache1_preload_addr::L1_ICACHE1_PRELOAD_ADDR_SPEC>;
1740#[doc = "L1 instruction Cache 1 preload address configure register"]
1741pub mod l1_icache1_preload_addr;
1742#[doc = "L1_ICACHE1_PRELOAD_SIZE (rw) register accessor: L1 instruction Cache 1 preload size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_preload_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_preload_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache1_preload_size`] module"]
1743pub type L1_ICACHE1_PRELOAD_SIZE =
1744 crate::Reg<l1_icache1_preload_size::L1_ICACHE1_PRELOAD_SIZE_SPEC>;
1745#[doc = "L1 instruction Cache 1 preload size configure register"]
1746pub mod l1_icache1_preload_size;
1747#[doc = "L1_ICACHE2_PRELOAD_CTRL (r) register accessor: L1 instruction Cache 2 preload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_preload_ctrl::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache2_preload_ctrl`] module"]
1748pub type L1_ICACHE2_PRELOAD_CTRL =
1749 crate::Reg<l1_icache2_preload_ctrl::L1_ICACHE2_PRELOAD_CTRL_SPEC>;
1750#[doc = "L1 instruction Cache 2 preload-operation control register"]
1751pub mod l1_icache2_preload_ctrl;
1752#[doc = "L1_ICACHE2_PRELOAD_ADDR (r) register accessor: L1 instruction Cache 2 preload address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_preload_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache2_preload_addr`] module"]
1753pub type L1_ICACHE2_PRELOAD_ADDR =
1754 crate::Reg<l1_icache2_preload_addr::L1_ICACHE2_PRELOAD_ADDR_SPEC>;
1755#[doc = "L1 instruction Cache 2 preload address configure register"]
1756pub mod l1_icache2_preload_addr;
1757#[doc = "L1_ICACHE2_PRELOAD_SIZE (r) register accessor: L1 instruction Cache 2 preload size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_preload_size::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache2_preload_size`] module"]
1758pub type L1_ICACHE2_PRELOAD_SIZE =
1759 crate::Reg<l1_icache2_preload_size::L1_ICACHE2_PRELOAD_SIZE_SPEC>;
1760#[doc = "L1 instruction Cache 2 preload size configure register"]
1761pub mod l1_icache2_preload_size;
1762#[doc = "L1_ICACHE3_PRELOAD_CTRL (r) register accessor: L1 instruction Cache 3 preload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_preload_ctrl::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache3_preload_ctrl`] module"]
1763pub type L1_ICACHE3_PRELOAD_CTRL =
1764 crate::Reg<l1_icache3_preload_ctrl::L1_ICACHE3_PRELOAD_CTRL_SPEC>;
1765#[doc = "L1 instruction Cache 3 preload-operation control register"]
1766pub mod l1_icache3_preload_ctrl;
1767#[doc = "L1_ICACHE3_PRELOAD_ADDR (r) register accessor: L1 instruction Cache 3 preload address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_preload_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache3_preload_addr`] module"]
1768pub type L1_ICACHE3_PRELOAD_ADDR =
1769 crate::Reg<l1_icache3_preload_addr::L1_ICACHE3_PRELOAD_ADDR_SPEC>;
1770#[doc = "L1 instruction Cache 3 preload address configure register"]
1771pub mod l1_icache3_preload_addr;
1772#[doc = "L1_ICACHE3_PRELOAD_SIZE (r) register accessor: L1 instruction Cache 3 preload size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_preload_size::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache3_preload_size`] module"]
1773pub type L1_ICACHE3_PRELOAD_SIZE =
1774 crate::Reg<l1_icache3_preload_size::L1_ICACHE3_PRELOAD_SIZE_SPEC>;
1775#[doc = "L1 instruction Cache 3 preload size configure register"]
1776pub mod l1_icache3_preload_size;
1777#[doc = "L1_DCACHE_PRELOAD_CTRL (rw) register accessor: L1 data Cache preload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_preload_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_preload_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_preload_ctrl`] module"]
1778pub type L1_DCACHE_PRELOAD_CTRL = crate::Reg<l1_dcache_preload_ctrl::L1_DCACHE_PRELOAD_CTRL_SPEC>;
1779#[doc = "L1 data Cache preload-operation control register"]
1780pub mod l1_dcache_preload_ctrl;
1781#[doc = "L1_DCACHE_PRELOAD_ADDR (rw) register accessor: L1 data Cache preload address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_preload_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_preload_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_preload_addr`] module"]
1782pub type L1_DCACHE_PRELOAD_ADDR = crate::Reg<l1_dcache_preload_addr::L1_DCACHE_PRELOAD_ADDR_SPEC>;
1783#[doc = "L1 data Cache preload address configure register"]
1784pub mod l1_dcache_preload_addr;
1785#[doc = "L1_DCACHE_PRELOAD_SIZE (rw) register accessor: L1 data Cache preload size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_preload_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_preload_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_preload_size`] module"]
1786pub type L1_DCACHE_PRELOAD_SIZE = crate::Reg<l1_dcache_preload_size::L1_DCACHE_PRELOAD_SIZE_SPEC>;
1787#[doc = "L1 data Cache preload size configure register"]
1788pub mod l1_dcache_preload_size;
1789#[doc = "L1_ICACHE0_AUTOLOAD_CTRL (rw) register accessor: L1 instruction Cache 0 autoload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_autoload_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_autoload_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache0_autoload_ctrl`] module"]
1790pub type L1_ICACHE0_AUTOLOAD_CTRL =
1791 crate::Reg<l1_icache0_autoload_ctrl::L1_ICACHE0_AUTOLOAD_CTRL_SPEC>;
1792#[doc = "L1 instruction Cache 0 autoload-operation control register"]
1793pub mod l1_icache0_autoload_ctrl;
1794#[doc = "L1_ICACHE0_AUTOLOAD_SCT0_ADDR (rw) register accessor: L1 instruction Cache 0 autoload section 0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_autoload_sct0_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_autoload_sct0_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache0_autoload_sct0_addr`] module"]
1795pub type L1_ICACHE0_AUTOLOAD_SCT0_ADDR =
1796 crate::Reg<l1_icache0_autoload_sct0_addr::L1_ICACHE0_AUTOLOAD_SCT0_ADDR_SPEC>;
1797#[doc = "L1 instruction Cache 0 autoload section 0 address configure register"]
1798pub mod l1_icache0_autoload_sct0_addr;
1799#[doc = "L1_ICACHE0_AUTOLOAD_SCT0_SIZE (rw) register accessor: L1 instruction Cache 0 autoload section 0 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_autoload_sct0_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_autoload_sct0_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache0_autoload_sct0_size`] module"]
1800pub type L1_ICACHE0_AUTOLOAD_SCT0_SIZE =
1801 crate::Reg<l1_icache0_autoload_sct0_size::L1_ICACHE0_AUTOLOAD_SCT0_SIZE_SPEC>;
1802#[doc = "L1 instruction Cache 0 autoload section 0 size configure register"]
1803pub mod l1_icache0_autoload_sct0_size;
1804#[doc = "L1_ICACHE0_AUTOLOAD_SCT1_ADDR (rw) register accessor: L1 instruction Cache 0 autoload section 1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_autoload_sct1_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_autoload_sct1_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache0_autoload_sct1_addr`] module"]
1805pub type L1_ICACHE0_AUTOLOAD_SCT1_ADDR =
1806 crate::Reg<l1_icache0_autoload_sct1_addr::L1_ICACHE0_AUTOLOAD_SCT1_ADDR_SPEC>;
1807#[doc = "L1 instruction Cache 0 autoload section 1 address configure register"]
1808pub mod l1_icache0_autoload_sct1_addr;
1809#[doc = "L1_ICACHE0_AUTOLOAD_SCT1_SIZE (rw) register accessor: L1 instruction Cache 0 autoload section 1 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_autoload_sct1_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_autoload_sct1_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache0_autoload_sct1_size`] module"]
1810pub type L1_ICACHE0_AUTOLOAD_SCT1_SIZE =
1811 crate::Reg<l1_icache0_autoload_sct1_size::L1_ICACHE0_AUTOLOAD_SCT1_SIZE_SPEC>;
1812#[doc = "L1 instruction Cache 0 autoload section 1 size configure register"]
1813pub mod l1_icache0_autoload_sct1_size;
1814#[doc = "L1_ICACHE1_AUTOLOAD_CTRL (rw) register accessor: L1 instruction Cache 1 autoload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_autoload_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_autoload_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache1_autoload_ctrl`] module"]
1815pub type L1_ICACHE1_AUTOLOAD_CTRL =
1816 crate::Reg<l1_icache1_autoload_ctrl::L1_ICACHE1_AUTOLOAD_CTRL_SPEC>;
1817#[doc = "L1 instruction Cache 1 autoload-operation control register"]
1818pub mod l1_icache1_autoload_ctrl;
1819#[doc = "L1_ICACHE1_AUTOLOAD_SCT0_ADDR (rw) register accessor: L1 instruction Cache 1 autoload section 0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_autoload_sct0_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_autoload_sct0_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache1_autoload_sct0_addr`] module"]
1820pub type L1_ICACHE1_AUTOLOAD_SCT0_ADDR =
1821 crate::Reg<l1_icache1_autoload_sct0_addr::L1_ICACHE1_AUTOLOAD_SCT0_ADDR_SPEC>;
1822#[doc = "L1 instruction Cache 1 autoload section 0 address configure register"]
1823pub mod l1_icache1_autoload_sct0_addr;
1824#[doc = "L1_ICACHE1_AUTOLOAD_SCT0_SIZE (rw) register accessor: L1 instruction Cache 1 autoload section 0 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_autoload_sct0_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_autoload_sct0_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache1_autoload_sct0_size`] module"]
1825pub type L1_ICACHE1_AUTOLOAD_SCT0_SIZE =
1826 crate::Reg<l1_icache1_autoload_sct0_size::L1_ICACHE1_AUTOLOAD_SCT0_SIZE_SPEC>;
1827#[doc = "L1 instruction Cache 1 autoload section 0 size configure register"]
1828pub mod l1_icache1_autoload_sct0_size;
1829#[doc = "L1_ICACHE1_AUTOLOAD_SCT1_ADDR (rw) register accessor: L1 instruction Cache 1 autoload section 1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_autoload_sct1_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_autoload_sct1_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache1_autoload_sct1_addr`] module"]
1830pub type L1_ICACHE1_AUTOLOAD_SCT1_ADDR =
1831 crate::Reg<l1_icache1_autoload_sct1_addr::L1_ICACHE1_AUTOLOAD_SCT1_ADDR_SPEC>;
1832#[doc = "L1 instruction Cache 1 autoload section 1 address configure register"]
1833pub mod l1_icache1_autoload_sct1_addr;
1834#[doc = "L1_ICACHE1_AUTOLOAD_SCT1_SIZE (rw) register accessor: L1 instruction Cache 1 autoload section 1 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_autoload_sct1_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_autoload_sct1_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache1_autoload_sct1_size`] module"]
1835pub type L1_ICACHE1_AUTOLOAD_SCT1_SIZE =
1836 crate::Reg<l1_icache1_autoload_sct1_size::L1_ICACHE1_AUTOLOAD_SCT1_SIZE_SPEC>;
1837#[doc = "L1 instruction Cache 1 autoload section 1 size configure register"]
1838pub mod l1_icache1_autoload_sct1_size;
1839#[doc = "L1_ICACHE2_AUTOLOAD_CTRL (r) register accessor: L1 instruction Cache 2 autoload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_autoload_ctrl::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache2_autoload_ctrl`] module"]
1840pub type L1_ICACHE2_AUTOLOAD_CTRL =
1841 crate::Reg<l1_icache2_autoload_ctrl::L1_ICACHE2_AUTOLOAD_CTRL_SPEC>;
1842#[doc = "L1 instruction Cache 2 autoload-operation control register"]
1843pub mod l1_icache2_autoload_ctrl;
1844#[doc = "L1_ICACHE2_AUTOLOAD_SCT0_ADDR (r) register accessor: L1 instruction Cache 2 autoload section 0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_autoload_sct0_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache2_autoload_sct0_addr`] module"]
1845pub type L1_ICACHE2_AUTOLOAD_SCT0_ADDR =
1846 crate::Reg<l1_icache2_autoload_sct0_addr::L1_ICACHE2_AUTOLOAD_SCT0_ADDR_SPEC>;
1847#[doc = "L1 instruction Cache 2 autoload section 0 address configure register"]
1848pub mod l1_icache2_autoload_sct0_addr;
1849#[doc = "L1_ICACHE2_AUTOLOAD_SCT0_SIZE (r) register accessor: L1 instruction Cache 2 autoload section 0 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_autoload_sct0_size::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache2_autoload_sct0_size`] module"]
1850pub type L1_ICACHE2_AUTOLOAD_SCT0_SIZE =
1851 crate::Reg<l1_icache2_autoload_sct0_size::L1_ICACHE2_AUTOLOAD_SCT0_SIZE_SPEC>;
1852#[doc = "L1 instruction Cache 2 autoload section 0 size configure register"]
1853pub mod l1_icache2_autoload_sct0_size;
1854#[doc = "L1_ICACHE2_AUTOLOAD_SCT1_ADDR (r) register accessor: L1 instruction Cache 2 autoload section 1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_autoload_sct1_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache2_autoload_sct1_addr`] module"]
1855pub type L1_ICACHE2_AUTOLOAD_SCT1_ADDR =
1856 crate::Reg<l1_icache2_autoload_sct1_addr::L1_ICACHE2_AUTOLOAD_SCT1_ADDR_SPEC>;
1857#[doc = "L1 instruction Cache 2 autoload section 1 address configure register"]
1858pub mod l1_icache2_autoload_sct1_addr;
1859#[doc = "L1_ICACHE2_AUTOLOAD_SCT1_SIZE (r) register accessor: L1 instruction Cache 2 autoload section 1 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_autoload_sct1_size::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache2_autoload_sct1_size`] module"]
1860pub type L1_ICACHE2_AUTOLOAD_SCT1_SIZE =
1861 crate::Reg<l1_icache2_autoload_sct1_size::L1_ICACHE2_AUTOLOAD_SCT1_SIZE_SPEC>;
1862#[doc = "L1 instruction Cache 2 autoload section 1 size configure register"]
1863pub mod l1_icache2_autoload_sct1_size;
1864#[doc = "L1_ICACHE3_AUTOLOAD_CTRL (r) register accessor: L1 instruction Cache 3 autoload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_autoload_ctrl::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache3_autoload_ctrl`] module"]
1865pub type L1_ICACHE3_AUTOLOAD_CTRL =
1866 crate::Reg<l1_icache3_autoload_ctrl::L1_ICACHE3_AUTOLOAD_CTRL_SPEC>;
1867#[doc = "L1 instruction Cache 3 autoload-operation control register"]
1868pub mod l1_icache3_autoload_ctrl;
1869#[doc = "L1_ICACHE3_AUTOLOAD_SCT0_ADDR (r) register accessor: L1 instruction Cache 3 autoload section 0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_autoload_sct0_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache3_autoload_sct0_addr`] module"]
1870pub type L1_ICACHE3_AUTOLOAD_SCT0_ADDR =
1871 crate::Reg<l1_icache3_autoload_sct0_addr::L1_ICACHE3_AUTOLOAD_SCT0_ADDR_SPEC>;
1872#[doc = "L1 instruction Cache 3 autoload section 0 address configure register"]
1873pub mod l1_icache3_autoload_sct0_addr;
1874#[doc = "L1_ICACHE3_AUTOLOAD_SCT0_SIZE (r) register accessor: L1 instruction Cache 3 autoload section 0 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_autoload_sct0_size::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache3_autoload_sct0_size`] module"]
1875pub type L1_ICACHE3_AUTOLOAD_SCT0_SIZE =
1876 crate::Reg<l1_icache3_autoload_sct0_size::L1_ICACHE3_AUTOLOAD_SCT0_SIZE_SPEC>;
1877#[doc = "L1 instruction Cache 3 autoload section 0 size configure register"]
1878pub mod l1_icache3_autoload_sct0_size;
1879#[doc = "L1_ICACHE3_AUTOLOAD_SCT1_ADDR (r) register accessor: L1 instruction Cache 3 autoload section 1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_autoload_sct1_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache3_autoload_sct1_addr`] module"]
1880pub type L1_ICACHE3_AUTOLOAD_SCT1_ADDR =
1881 crate::Reg<l1_icache3_autoload_sct1_addr::L1_ICACHE3_AUTOLOAD_SCT1_ADDR_SPEC>;
1882#[doc = "L1 instruction Cache 3 autoload section 1 address configure register"]
1883pub mod l1_icache3_autoload_sct1_addr;
1884#[doc = "L1_ICACHE3_AUTOLOAD_SCT1_SIZE (r) register accessor: L1 instruction Cache 3 autoload section 1 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_autoload_sct1_size::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache3_autoload_sct1_size`] module"]
1885pub type L1_ICACHE3_AUTOLOAD_SCT1_SIZE =
1886 crate::Reg<l1_icache3_autoload_sct1_size::L1_ICACHE3_AUTOLOAD_SCT1_SIZE_SPEC>;
1887#[doc = "L1 instruction Cache 3 autoload section 1 size configure register"]
1888pub mod l1_icache3_autoload_sct1_size;
1889#[doc = "L1_DCACHE_AUTOLOAD_CTRL (rw) register accessor: L1 data Cache autoload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_autoload_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_autoload_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_autoload_ctrl`] module"]
1890pub type L1_DCACHE_AUTOLOAD_CTRL =
1891 crate::Reg<l1_dcache_autoload_ctrl::L1_DCACHE_AUTOLOAD_CTRL_SPEC>;
1892#[doc = "L1 data Cache autoload-operation control register"]
1893pub mod l1_dcache_autoload_ctrl;
1894#[doc = "L1_DCACHE_AUTOLOAD_SCT0_ADDR (rw) register accessor: L1 data Cache autoload section 0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_autoload_sct0_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_autoload_sct0_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_autoload_sct0_addr`] module"]
1895pub type L1_DCACHE_AUTOLOAD_SCT0_ADDR =
1896 crate::Reg<l1_dcache_autoload_sct0_addr::L1_DCACHE_AUTOLOAD_SCT0_ADDR_SPEC>;
1897#[doc = "L1 data Cache autoload section 0 address configure register"]
1898pub mod l1_dcache_autoload_sct0_addr;
1899#[doc = "L1_DCACHE_AUTOLOAD_SCT0_SIZE (rw) register accessor: L1 data Cache autoload section 0 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_autoload_sct0_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_autoload_sct0_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_autoload_sct0_size`] module"]
1900pub type L1_DCACHE_AUTOLOAD_SCT0_SIZE =
1901 crate::Reg<l1_dcache_autoload_sct0_size::L1_DCACHE_AUTOLOAD_SCT0_SIZE_SPEC>;
1902#[doc = "L1 data Cache autoload section 0 size configure register"]
1903pub mod l1_dcache_autoload_sct0_size;
1904#[doc = "L1_DCACHE_AUTOLOAD_SCT1_ADDR (rw) register accessor: L1 data Cache autoload section 1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_autoload_sct1_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_autoload_sct1_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_autoload_sct1_addr`] module"]
1905pub type L1_DCACHE_AUTOLOAD_SCT1_ADDR =
1906 crate::Reg<l1_dcache_autoload_sct1_addr::L1_DCACHE_AUTOLOAD_SCT1_ADDR_SPEC>;
1907#[doc = "L1 data Cache autoload section 1 address configure register"]
1908pub mod l1_dcache_autoload_sct1_addr;
1909#[doc = "L1_DCACHE_AUTOLOAD_SCT1_SIZE (rw) register accessor: L1 data Cache autoload section 1 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_autoload_sct1_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_autoload_sct1_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_autoload_sct1_size`] module"]
1910pub type L1_DCACHE_AUTOLOAD_SCT1_SIZE =
1911 crate::Reg<l1_dcache_autoload_sct1_size::L1_DCACHE_AUTOLOAD_SCT1_SIZE_SPEC>;
1912#[doc = "L1 data Cache autoload section 1 size configure register"]
1913pub mod l1_dcache_autoload_sct1_size;
1914#[doc = "L1_DCACHE_AUTOLOAD_SCT2_ADDR (rw) register accessor: L1 data Cache autoload section 2 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_autoload_sct2_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_autoload_sct2_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_autoload_sct2_addr`] module"]
1915pub type L1_DCACHE_AUTOLOAD_SCT2_ADDR =
1916 crate::Reg<l1_dcache_autoload_sct2_addr::L1_DCACHE_AUTOLOAD_SCT2_ADDR_SPEC>;
1917#[doc = "L1 data Cache autoload section 2 address configure register"]
1918pub mod l1_dcache_autoload_sct2_addr;
1919#[doc = "L1_DCACHE_AUTOLOAD_SCT2_SIZE (rw) register accessor: L1 data Cache autoload section 2 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_autoload_sct2_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_autoload_sct2_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_autoload_sct2_size`] module"]
1920pub type L1_DCACHE_AUTOLOAD_SCT2_SIZE =
1921 crate::Reg<l1_dcache_autoload_sct2_size::L1_DCACHE_AUTOLOAD_SCT2_SIZE_SPEC>;
1922#[doc = "L1 data Cache autoload section 2 size configure register"]
1923pub mod l1_dcache_autoload_sct2_size;
1924#[doc = "L1_DCACHE_AUTOLOAD_SCT3_ADDR (rw) register accessor: L1 data Cache autoload section 1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_autoload_sct3_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_autoload_sct3_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_autoload_sct3_addr`] module"]
1925pub type L1_DCACHE_AUTOLOAD_SCT3_ADDR =
1926 crate::Reg<l1_dcache_autoload_sct3_addr::L1_DCACHE_AUTOLOAD_SCT3_ADDR_SPEC>;
1927#[doc = "L1 data Cache autoload section 1 address configure register"]
1928pub mod l1_dcache_autoload_sct3_addr;
1929#[doc = "L1_DCACHE_AUTOLOAD_SCT3_SIZE (rw) register accessor: L1 data Cache autoload section 1 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_autoload_sct3_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_autoload_sct3_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_autoload_sct3_size`] module"]
1930pub type L1_DCACHE_AUTOLOAD_SCT3_SIZE =
1931 crate::Reg<l1_dcache_autoload_sct3_size::L1_DCACHE_AUTOLOAD_SCT3_SIZE_SPEC>;
1932#[doc = "L1 data Cache autoload section 1 size configure register"]
1933pub mod l1_dcache_autoload_sct3_size;
1934#[doc = "L1_CACHE_ACS_CNT_INT_ENA (rw) register accessor: Cache Access Counter Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_cnt_int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_acs_cnt_int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_acs_cnt_int_ena`] module"]
1935pub type L1_CACHE_ACS_CNT_INT_ENA =
1936 crate::Reg<l1_cache_acs_cnt_int_ena::L1_CACHE_ACS_CNT_INT_ENA_SPEC>;
1937#[doc = "Cache Access Counter Interrupt enable register"]
1938pub mod l1_cache_acs_cnt_int_ena;
1939#[doc = "L1_CACHE_ACS_CNT_INT_CLR (rw) register accessor: Cache Access Counter Interrupt clear register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_cnt_int_clr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_acs_cnt_int_clr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_acs_cnt_int_clr`] module"]
1940pub type L1_CACHE_ACS_CNT_INT_CLR =
1941 crate::Reg<l1_cache_acs_cnt_int_clr::L1_CACHE_ACS_CNT_INT_CLR_SPEC>;
1942#[doc = "Cache Access Counter Interrupt clear register"]
1943pub mod l1_cache_acs_cnt_int_clr;
1944#[doc = "L1_CACHE_ACS_CNT_INT_RAW (rw) register accessor: Cache Access Counter Interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_cnt_int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_acs_cnt_int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_acs_cnt_int_raw`] module"]
1945pub type L1_CACHE_ACS_CNT_INT_RAW =
1946 crate::Reg<l1_cache_acs_cnt_int_raw::L1_CACHE_ACS_CNT_INT_RAW_SPEC>;
1947#[doc = "Cache Access Counter Interrupt raw register"]
1948pub mod l1_cache_acs_cnt_int_raw;
1949#[doc = "L1_CACHE_ACS_CNT_INT_ST (r) register accessor: Cache Access Counter Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_cnt_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_acs_cnt_int_st`] module"]
1950pub type L1_CACHE_ACS_CNT_INT_ST =
1951 crate::Reg<l1_cache_acs_cnt_int_st::L1_CACHE_ACS_CNT_INT_ST_SPEC>;
1952#[doc = "Cache Access Counter Interrupt status register"]
1953pub mod l1_cache_acs_cnt_int_st;
1954#[doc = "L1_CACHE_ACS_FAIL_CTRL (rw) register accessor: Cache Access Fail Configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_fail_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_acs_fail_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_acs_fail_ctrl`] module"]
1955pub type L1_CACHE_ACS_FAIL_CTRL = crate::Reg<l1_cache_acs_fail_ctrl::L1_CACHE_ACS_FAIL_CTRL_SPEC>;
1956#[doc = "Cache Access Fail Configuration register"]
1957pub mod l1_cache_acs_fail_ctrl;
1958#[doc = "L1_CACHE_ACS_FAIL_INT_ENA (rw) register accessor: Cache Access Fail Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_fail_int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_acs_fail_int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_acs_fail_int_ena`] module"]
1959pub type L1_CACHE_ACS_FAIL_INT_ENA =
1960 crate::Reg<l1_cache_acs_fail_int_ena::L1_CACHE_ACS_FAIL_INT_ENA_SPEC>;
1961#[doc = "Cache Access Fail Interrupt enable register"]
1962pub mod l1_cache_acs_fail_int_ena;
1963#[doc = "L1_CACHE_ACS_FAIL_INT_CLR (rw) register accessor: L1-Cache Access Fail Interrupt clear register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_fail_int_clr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_acs_fail_int_clr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_acs_fail_int_clr`] module"]
1964pub type L1_CACHE_ACS_FAIL_INT_CLR =
1965 crate::Reg<l1_cache_acs_fail_int_clr::L1_CACHE_ACS_FAIL_INT_CLR_SPEC>;
1966#[doc = "L1-Cache Access Fail Interrupt clear register"]
1967pub mod l1_cache_acs_fail_int_clr;
1968#[doc = "L1_CACHE_ACS_FAIL_INT_RAW (rw) register accessor: Cache Access Fail Interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_fail_int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_acs_fail_int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_acs_fail_int_raw`] module"]
1969pub type L1_CACHE_ACS_FAIL_INT_RAW =
1970 crate::Reg<l1_cache_acs_fail_int_raw::L1_CACHE_ACS_FAIL_INT_RAW_SPEC>;
1971#[doc = "Cache Access Fail Interrupt raw register"]
1972pub mod l1_cache_acs_fail_int_raw;
1973#[doc = "L1_CACHE_ACS_FAIL_INT_ST (r) register accessor: Cache Access Fail Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_fail_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_acs_fail_int_st`] module"]
1974pub type L1_CACHE_ACS_FAIL_INT_ST =
1975 crate::Reg<l1_cache_acs_fail_int_st::L1_CACHE_ACS_FAIL_INT_ST_SPEC>;
1976#[doc = "Cache Access Fail Interrupt status register"]
1977pub mod l1_cache_acs_fail_int_st;
1978#[doc = "L1_CACHE_ACS_CNT_CTRL (rw) register accessor: Cache Access Counter enable and clear register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_cnt_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_acs_cnt_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_acs_cnt_ctrl`] module"]
1979pub type L1_CACHE_ACS_CNT_CTRL = crate::Reg<l1_cache_acs_cnt_ctrl::L1_CACHE_ACS_CNT_CTRL_SPEC>;
1980#[doc = "Cache Access Counter enable and clear register"]
1981pub mod l1_cache_acs_cnt_ctrl;
1982#[doc = "L1_IBUS0_ACS_HIT_CNT (r) register accessor: L1-ICache bus0 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus0_acs_hit_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_ibus0_acs_hit_cnt`] module"]
1983pub type L1_IBUS0_ACS_HIT_CNT = crate::Reg<l1_ibus0_acs_hit_cnt::L1_IBUS0_ACS_HIT_CNT_SPEC>;
1984#[doc = "L1-ICache bus0 Hit-Access Counter register"]
1985pub mod l1_ibus0_acs_hit_cnt;
1986#[doc = "L1_IBUS0_ACS_MISS_CNT (r) register accessor: L1-ICache bus0 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus0_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_ibus0_acs_miss_cnt`] module"]
1987pub type L1_IBUS0_ACS_MISS_CNT = crate::Reg<l1_ibus0_acs_miss_cnt::L1_IBUS0_ACS_MISS_CNT_SPEC>;
1988#[doc = "L1-ICache bus0 Miss-Access Counter register"]
1989pub mod l1_ibus0_acs_miss_cnt;
1990#[doc = "L1_IBUS0_ACS_CONFLICT_CNT (r) register accessor: L1-ICache bus0 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus0_acs_conflict_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_ibus0_acs_conflict_cnt`] module"]
1991pub type L1_IBUS0_ACS_CONFLICT_CNT =
1992 crate::Reg<l1_ibus0_acs_conflict_cnt::L1_IBUS0_ACS_CONFLICT_CNT_SPEC>;
1993#[doc = "L1-ICache bus0 Conflict-Access Counter register"]
1994pub mod l1_ibus0_acs_conflict_cnt;
1995#[doc = "L1_IBUS0_ACS_NXTLVL_RD_CNT (r) register accessor: L1-ICache bus0 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus0_acs_nxtlvl_rd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_ibus0_acs_nxtlvl_rd_cnt`] module"]
1996pub type L1_IBUS0_ACS_NXTLVL_RD_CNT =
1997 crate::Reg<l1_ibus0_acs_nxtlvl_rd_cnt::L1_IBUS0_ACS_NXTLVL_RD_CNT_SPEC>;
1998#[doc = "L1-ICache bus0 Next-Level-Access Counter register"]
1999pub mod l1_ibus0_acs_nxtlvl_rd_cnt;
2000#[doc = "L1_IBUS1_ACS_HIT_CNT (r) register accessor: L1-ICache bus1 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus1_acs_hit_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_ibus1_acs_hit_cnt`] module"]
2001pub type L1_IBUS1_ACS_HIT_CNT = crate::Reg<l1_ibus1_acs_hit_cnt::L1_IBUS1_ACS_HIT_CNT_SPEC>;
2002#[doc = "L1-ICache bus1 Hit-Access Counter register"]
2003pub mod l1_ibus1_acs_hit_cnt;
2004#[doc = "L1_IBUS1_ACS_MISS_CNT (r) register accessor: L1-ICache bus1 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus1_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_ibus1_acs_miss_cnt`] module"]
2005pub type L1_IBUS1_ACS_MISS_CNT = crate::Reg<l1_ibus1_acs_miss_cnt::L1_IBUS1_ACS_MISS_CNT_SPEC>;
2006#[doc = "L1-ICache bus1 Miss-Access Counter register"]
2007pub mod l1_ibus1_acs_miss_cnt;
2008#[doc = "L1_IBUS1_ACS_CONFLICT_CNT (r) register accessor: L1-ICache bus1 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus1_acs_conflict_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_ibus1_acs_conflict_cnt`] module"]
2009pub type L1_IBUS1_ACS_CONFLICT_CNT =
2010 crate::Reg<l1_ibus1_acs_conflict_cnt::L1_IBUS1_ACS_CONFLICT_CNT_SPEC>;
2011#[doc = "L1-ICache bus1 Conflict-Access Counter register"]
2012pub mod l1_ibus1_acs_conflict_cnt;
2013#[doc = "L1_IBUS1_ACS_NXTLVL_RD_CNT (r) register accessor: L1-ICache bus1 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus1_acs_nxtlvl_rd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_ibus1_acs_nxtlvl_rd_cnt`] module"]
2014pub type L1_IBUS1_ACS_NXTLVL_RD_CNT =
2015 crate::Reg<l1_ibus1_acs_nxtlvl_rd_cnt::L1_IBUS1_ACS_NXTLVL_RD_CNT_SPEC>;
2016#[doc = "L1-ICache bus1 Next-Level-Access Counter register"]
2017pub mod l1_ibus1_acs_nxtlvl_rd_cnt;
2018#[doc = "L1_IBUS2_ACS_HIT_CNT (r) register accessor: L1-ICache bus2 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus2_acs_hit_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_ibus2_acs_hit_cnt`] module"]
2019pub type L1_IBUS2_ACS_HIT_CNT = crate::Reg<l1_ibus2_acs_hit_cnt::L1_IBUS2_ACS_HIT_CNT_SPEC>;
2020#[doc = "L1-ICache bus2 Hit-Access Counter register"]
2021pub mod l1_ibus2_acs_hit_cnt;
2022#[doc = "L1_IBUS2_ACS_MISS_CNT (r) register accessor: L1-ICache bus2 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus2_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_ibus2_acs_miss_cnt`] module"]
2023pub type L1_IBUS2_ACS_MISS_CNT = crate::Reg<l1_ibus2_acs_miss_cnt::L1_IBUS2_ACS_MISS_CNT_SPEC>;
2024#[doc = "L1-ICache bus2 Miss-Access Counter register"]
2025pub mod l1_ibus2_acs_miss_cnt;
2026#[doc = "L1_IBUS2_ACS_CONFLICT_CNT (r) register accessor: L1-ICache bus2 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus2_acs_conflict_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_ibus2_acs_conflict_cnt`] module"]
2027pub type L1_IBUS2_ACS_CONFLICT_CNT =
2028 crate::Reg<l1_ibus2_acs_conflict_cnt::L1_IBUS2_ACS_CONFLICT_CNT_SPEC>;
2029#[doc = "L1-ICache bus2 Conflict-Access Counter register"]
2030pub mod l1_ibus2_acs_conflict_cnt;
2031#[doc = "L1_IBUS2_ACS_NXTLVL_RD_CNT (r) register accessor: L1-ICache bus2 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus2_acs_nxtlvl_rd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_ibus2_acs_nxtlvl_rd_cnt`] module"]
2032pub type L1_IBUS2_ACS_NXTLVL_RD_CNT =
2033 crate::Reg<l1_ibus2_acs_nxtlvl_rd_cnt::L1_IBUS2_ACS_NXTLVL_RD_CNT_SPEC>;
2034#[doc = "L1-ICache bus2 Next-Level-Access Counter register"]
2035pub mod l1_ibus2_acs_nxtlvl_rd_cnt;
2036#[doc = "L1_IBUS3_ACS_HIT_CNT (r) register accessor: L1-ICache bus3 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus3_acs_hit_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_ibus3_acs_hit_cnt`] module"]
2037pub type L1_IBUS3_ACS_HIT_CNT = crate::Reg<l1_ibus3_acs_hit_cnt::L1_IBUS3_ACS_HIT_CNT_SPEC>;
2038#[doc = "L1-ICache bus3 Hit-Access Counter register"]
2039pub mod l1_ibus3_acs_hit_cnt;
2040#[doc = "L1_IBUS3_ACS_MISS_CNT (r) register accessor: L1-ICache bus3 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus3_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_ibus3_acs_miss_cnt`] module"]
2041pub type L1_IBUS3_ACS_MISS_CNT = crate::Reg<l1_ibus3_acs_miss_cnt::L1_IBUS3_ACS_MISS_CNT_SPEC>;
2042#[doc = "L1-ICache bus3 Miss-Access Counter register"]
2043pub mod l1_ibus3_acs_miss_cnt;
2044#[doc = "L1_IBUS3_ACS_CONFLICT_CNT (r) register accessor: L1-ICache bus3 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus3_acs_conflict_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_ibus3_acs_conflict_cnt`] module"]
2045pub type L1_IBUS3_ACS_CONFLICT_CNT =
2046 crate::Reg<l1_ibus3_acs_conflict_cnt::L1_IBUS3_ACS_CONFLICT_CNT_SPEC>;
2047#[doc = "L1-ICache bus3 Conflict-Access Counter register"]
2048pub mod l1_ibus3_acs_conflict_cnt;
2049#[doc = "L1_IBUS3_ACS_NXTLVL_RD_CNT (r) register accessor: L1-ICache bus3 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus3_acs_nxtlvl_rd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_ibus3_acs_nxtlvl_rd_cnt`] module"]
2050pub type L1_IBUS3_ACS_NXTLVL_RD_CNT =
2051 crate::Reg<l1_ibus3_acs_nxtlvl_rd_cnt::L1_IBUS3_ACS_NXTLVL_RD_CNT_SPEC>;
2052#[doc = "L1-ICache bus3 Next-Level-Access Counter register"]
2053pub mod l1_ibus3_acs_nxtlvl_rd_cnt;
2054#[doc = "L1_DBUS0_ACS_HIT_CNT (r) register accessor: L1-DCache bus0 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus0_acs_hit_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus0_acs_hit_cnt`] module"]
2055pub type L1_DBUS0_ACS_HIT_CNT = crate::Reg<l1_dbus0_acs_hit_cnt::L1_DBUS0_ACS_HIT_CNT_SPEC>;
2056#[doc = "L1-DCache bus0 Hit-Access Counter register"]
2057pub mod l1_dbus0_acs_hit_cnt;
2058#[doc = "L1_DBUS0_ACS_MISS_CNT (r) register accessor: L1-DCache bus0 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus0_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus0_acs_miss_cnt`] module"]
2059pub type L1_DBUS0_ACS_MISS_CNT = crate::Reg<l1_dbus0_acs_miss_cnt::L1_DBUS0_ACS_MISS_CNT_SPEC>;
2060#[doc = "L1-DCache bus0 Miss-Access Counter register"]
2061pub mod l1_dbus0_acs_miss_cnt;
2062#[doc = "L1_DBUS0_ACS_CONFLICT_CNT (r) register accessor: L1-DCache bus0 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus0_acs_conflict_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus0_acs_conflict_cnt`] module"]
2063pub type L1_DBUS0_ACS_CONFLICT_CNT =
2064 crate::Reg<l1_dbus0_acs_conflict_cnt::L1_DBUS0_ACS_CONFLICT_CNT_SPEC>;
2065#[doc = "L1-DCache bus0 Conflict-Access Counter register"]
2066pub mod l1_dbus0_acs_conflict_cnt;
2067#[doc = "L1_DBUS0_ACS_NXTLVL_RD_CNT (r) register accessor: L1-DCache bus0 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus0_acs_nxtlvl_rd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus0_acs_nxtlvl_rd_cnt`] module"]
2068pub type L1_DBUS0_ACS_NXTLVL_RD_CNT =
2069 crate::Reg<l1_dbus0_acs_nxtlvl_rd_cnt::L1_DBUS0_ACS_NXTLVL_RD_CNT_SPEC>;
2070#[doc = "L1-DCache bus0 Next-Level-Access Counter register"]
2071pub mod l1_dbus0_acs_nxtlvl_rd_cnt;
2072#[doc = "L1_DBUS0_ACS_NXTLVL_WR_CNT (r) register accessor: L1-DCache bus0 WB-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus0_acs_nxtlvl_wr_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus0_acs_nxtlvl_wr_cnt`] module"]
2073pub type L1_DBUS0_ACS_NXTLVL_WR_CNT =
2074 crate::Reg<l1_dbus0_acs_nxtlvl_wr_cnt::L1_DBUS0_ACS_NXTLVL_WR_CNT_SPEC>;
2075#[doc = "L1-DCache bus0 WB-Access Counter register"]
2076pub mod l1_dbus0_acs_nxtlvl_wr_cnt;
2077#[doc = "L1_DBUS1_ACS_HIT_CNT (r) register accessor: L1-DCache bus1 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus1_acs_hit_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus1_acs_hit_cnt`] module"]
2078pub type L1_DBUS1_ACS_HIT_CNT = crate::Reg<l1_dbus1_acs_hit_cnt::L1_DBUS1_ACS_HIT_CNT_SPEC>;
2079#[doc = "L1-DCache bus1 Hit-Access Counter register"]
2080pub mod l1_dbus1_acs_hit_cnt;
2081#[doc = "L1_DBUS1_ACS_MISS_CNT (r) register accessor: L1-DCache bus1 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus1_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus1_acs_miss_cnt`] module"]
2082pub type L1_DBUS1_ACS_MISS_CNT = crate::Reg<l1_dbus1_acs_miss_cnt::L1_DBUS1_ACS_MISS_CNT_SPEC>;
2083#[doc = "L1-DCache bus1 Miss-Access Counter register"]
2084pub mod l1_dbus1_acs_miss_cnt;
2085#[doc = "L1_DBUS1_ACS_CONFLICT_CNT (r) register accessor: L1-DCache bus1 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus1_acs_conflict_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus1_acs_conflict_cnt`] module"]
2086pub type L1_DBUS1_ACS_CONFLICT_CNT =
2087 crate::Reg<l1_dbus1_acs_conflict_cnt::L1_DBUS1_ACS_CONFLICT_CNT_SPEC>;
2088#[doc = "L1-DCache bus1 Conflict-Access Counter register"]
2089pub mod l1_dbus1_acs_conflict_cnt;
2090#[doc = "L1_DBUS1_ACS_NXTLVL_RD_CNT (r) register accessor: L1-DCache bus1 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus1_acs_nxtlvl_rd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus1_acs_nxtlvl_rd_cnt`] module"]
2091pub type L1_DBUS1_ACS_NXTLVL_RD_CNT =
2092 crate::Reg<l1_dbus1_acs_nxtlvl_rd_cnt::L1_DBUS1_ACS_NXTLVL_RD_CNT_SPEC>;
2093#[doc = "L1-DCache bus1 Next-Level-Access Counter register"]
2094pub mod l1_dbus1_acs_nxtlvl_rd_cnt;
2095#[doc = "L1_DBUS1_ACS_NXTLVL_WR_CNT (r) register accessor: L1-DCache bus1 WB-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus1_acs_nxtlvl_wr_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus1_acs_nxtlvl_wr_cnt`] module"]
2096pub type L1_DBUS1_ACS_NXTLVL_WR_CNT =
2097 crate::Reg<l1_dbus1_acs_nxtlvl_wr_cnt::L1_DBUS1_ACS_NXTLVL_WR_CNT_SPEC>;
2098#[doc = "L1-DCache bus1 WB-Access Counter register"]
2099pub mod l1_dbus1_acs_nxtlvl_wr_cnt;
2100#[doc = "L1_DBUS2_ACS_HIT_CNT (r) register accessor: L1-DCache bus2 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus2_acs_hit_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus2_acs_hit_cnt`] module"]
2101pub type L1_DBUS2_ACS_HIT_CNT = crate::Reg<l1_dbus2_acs_hit_cnt::L1_DBUS2_ACS_HIT_CNT_SPEC>;
2102#[doc = "L1-DCache bus2 Hit-Access Counter register"]
2103pub mod l1_dbus2_acs_hit_cnt;
2104#[doc = "L1_DBUS2_ACS_MISS_CNT (r) register accessor: L1-DCache bus2 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus2_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus2_acs_miss_cnt`] module"]
2105pub type L1_DBUS2_ACS_MISS_CNT = crate::Reg<l1_dbus2_acs_miss_cnt::L1_DBUS2_ACS_MISS_CNT_SPEC>;
2106#[doc = "L1-DCache bus2 Miss-Access Counter register"]
2107pub mod l1_dbus2_acs_miss_cnt;
2108#[doc = "L1_DBUS2_ACS_CONFLICT_CNT (r) register accessor: L1-DCache bus2 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus2_acs_conflict_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus2_acs_conflict_cnt`] module"]
2109pub type L1_DBUS2_ACS_CONFLICT_CNT =
2110 crate::Reg<l1_dbus2_acs_conflict_cnt::L1_DBUS2_ACS_CONFLICT_CNT_SPEC>;
2111#[doc = "L1-DCache bus2 Conflict-Access Counter register"]
2112pub mod l1_dbus2_acs_conflict_cnt;
2113#[doc = "L1_DBUS2_ACS_NXTLVL_RD_CNT (r) register accessor: L1-DCache bus2 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus2_acs_nxtlvl_rd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus2_acs_nxtlvl_rd_cnt`] module"]
2114pub type L1_DBUS2_ACS_NXTLVL_RD_CNT =
2115 crate::Reg<l1_dbus2_acs_nxtlvl_rd_cnt::L1_DBUS2_ACS_NXTLVL_RD_CNT_SPEC>;
2116#[doc = "L1-DCache bus2 Next-Level-Access Counter register"]
2117pub mod l1_dbus2_acs_nxtlvl_rd_cnt;
2118#[doc = "L1_DBUS2_ACS_NXTLVL_WR_CNT (r) register accessor: L1-DCache bus2 WB-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus2_acs_nxtlvl_wr_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus2_acs_nxtlvl_wr_cnt`] module"]
2119pub type L1_DBUS2_ACS_NXTLVL_WR_CNT =
2120 crate::Reg<l1_dbus2_acs_nxtlvl_wr_cnt::L1_DBUS2_ACS_NXTLVL_WR_CNT_SPEC>;
2121#[doc = "L1-DCache bus2 WB-Access Counter register"]
2122pub mod l1_dbus2_acs_nxtlvl_wr_cnt;
2123#[doc = "L1_DBUS3_ACS_HIT_CNT (r) register accessor: L1-DCache bus3 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus3_acs_hit_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus3_acs_hit_cnt`] module"]
2124pub type L1_DBUS3_ACS_HIT_CNT = crate::Reg<l1_dbus3_acs_hit_cnt::L1_DBUS3_ACS_HIT_CNT_SPEC>;
2125#[doc = "L1-DCache bus3 Hit-Access Counter register"]
2126pub mod l1_dbus3_acs_hit_cnt;
2127#[doc = "L1_DBUS3_ACS_MISS_CNT (r) register accessor: L1-DCache bus3 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus3_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus3_acs_miss_cnt`] module"]
2128pub type L1_DBUS3_ACS_MISS_CNT = crate::Reg<l1_dbus3_acs_miss_cnt::L1_DBUS3_ACS_MISS_CNT_SPEC>;
2129#[doc = "L1-DCache bus3 Miss-Access Counter register"]
2130pub mod l1_dbus3_acs_miss_cnt;
2131#[doc = "L1_DBUS3_ACS_CONFLICT_CNT (r) register accessor: L1-DCache bus3 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus3_acs_conflict_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus3_acs_conflict_cnt`] module"]
2132pub type L1_DBUS3_ACS_CONFLICT_CNT =
2133 crate::Reg<l1_dbus3_acs_conflict_cnt::L1_DBUS3_ACS_CONFLICT_CNT_SPEC>;
2134#[doc = "L1-DCache bus3 Conflict-Access Counter register"]
2135pub mod l1_dbus3_acs_conflict_cnt;
2136#[doc = "L1_DBUS3_ACS_NXTLVL_RD_CNT (r) register accessor: L1-DCache bus3 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus3_acs_nxtlvl_rd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus3_acs_nxtlvl_rd_cnt`] module"]
2137pub type L1_DBUS3_ACS_NXTLVL_RD_CNT =
2138 crate::Reg<l1_dbus3_acs_nxtlvl_rd_cnt::L1_DBUS3_ACS_NXTLVL_RD_CNT_SPEC>;
2139#[doc = "L1-DCache bus3 Next-Level-Access Counter register"]
2140pub mod l1_dbus3_acs_nxtlvl_rd_cnt;
2141#[doc = "L1_DBUS3_ACS_NXTLVL_WR_CNT (r) register accessor: L1-DCache bus3 WB-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus3_acs_nxtlvl_wr_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus3_acs_nxtlvl_wr_cnt`] module"]
2142pub type L1_DBUS3_ACS_NXTLVL_WR_CNT =
2143 crate::Reg<l1_dbus3_acs_nxtlvl_wr_cnt::L1_DBUS3_ACS_NXTLVL_WR_CNT_SPEC>;
2144#[doc = "L1-DCache bus3 WB-Access Counter register"]
2145pub mod l1_dbus3_acs_nxtlvl_wr_cnt;
2146#[doc = "L1_ICACHE0_ACS_FAIL_ID_ATTR (r) register accessor: L1-ICache0 Access Fail ID/attribution information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_acs_fail_id_attr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache0_acs_fail_id_attr`] module"]
2147pub type L1_ICACHE0_ACS_FAIL_ID_ATTR =
2148 crate::Reg<l1_icache0_acs_fail_id_attr::L1_ICACHE0_ACS_FAIL_ID_ATTR_SPEC>;
2149#[doc = "L1-ICache0 Access Fail ID/attribution information register"]
2150pub mod l1_icache0_acs_fail_id_attr;
2151#[doc = "L1_ICACHE0_ACS_FAIL_ADDR (r) register accessor: L1-ICache0 Access Fail Address information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_acs_fail_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache0_acs_fail_addr`] module"]
2152pub type L1_ICACHE0_ACS_FAIL_ADDR =
2153 crate::Reg<l1_icache0_acs_fail_addr::L1_ICACHE0_ACS_FAIL_ADDR_SPEC>;
2154#[doc = "L1-ICache0 Access Fail Address information register"]
2155pub mod l1_icache0_acs_fail_addr;
2156#[doc = "L1_ICACHE1_ACS_FAIL_ID_ATTR (r) register accessor: L1-ICache0 Access Fail ID/attribution information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_acs_fail_id_attr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache1_acs_fail_id_attr`] module"]
2157pub type L1_ICACHE1_ACS_FAIL_ID_ATTR =
2158 crate::Reg<l1_icache1_acs_fail_id_attr::L1_ICACHE1_ACS_FAIL_ID_ATTR_SPEC>;
2159#[doc = "L1-ICache0 Access Fail ID/attribution information register"]
2160pub mod l1_icache1_acs_fail_id_attr;
2161#[doc = "L1_ICACHE1_ACS_FAIL_ADDR (r) register accessor: L1-ICache0 Access Fail Address information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_acs_fail_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache1_acs_fail_addr`] module"]
2162pub type L1_ICACHE1_ACS_FAIL_ADDR =
2163 crate::Reg<l1_icache1_acs_fail_addr::L1_ICACHE1_ACS_FAIL_ADDR_SPEC>;
2164#[doc = "L1-ICache0 Access Fail Address information register"]
2165pub mod l1_icache1_acs_fail_addr;
2166#[doc = "L1_ICACHE2_ACS_FAIL_ID_ATTR (r) register accessor: L1-ICache0 Access Fail ID/attribution information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_acs_fail_id_attr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache2_acs_fail_id_attr`] module"]
2167pub type L1_ICACHE2_ACS_FAIL_ID_ATTR =
2168 crate::Reg<l1_icache2_acs_fail_id_attr::L1_ICACHE2_ACS_FAIL_ID_ATTR_SPEC>;
2169#[doc = "L1-ICache0 Access Fail ID/attribution information register"]
2170pub mod l1_icache2_acs_fail_id_attr;
2171#[doc = "L1_ICACHE2_ACS_FAIL_ADDR (r) register accessor: L1-ICache0 Access Fail Address information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_acs_fail_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache2_acs_fail_addr`] module"]
2172pub type L1_ICACHE2_ACS_FAIL_ADDR =
2173 crate::Reg<l1_icache2_acs_fail_addr::L1_ICACHE2_ACS_FAIL_ADDR_SPEC>;
2174#[doc = "L1-ICache0 Access Fail Address information register"]
2175pub mod l1_icache2_acs_fail_addr;
2176#[doc = "L1_ICACHE3_ACS_FAIL_ID_ATTR (r) register accessor: L1-ICache0 Access Fail ID/attribution information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_acs_fail_id_attr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache3_acs_fail_id_attr`] module"]
2177pub type L1_ICACHE3_ACS_FAIL_ID_ATTR =
2178 crate::Reg<l1_icache3_acs_fail_id_attr::L1_ICACHE3_ACS_FAIL_ID_ATTR_SPEC>;
2179#[doc = "L1-ICache0 Access Fail ID/attribution information register"]
2180pub mod l1_icache3_acs_fail_id_attr;
2181#[doc = "L1_ICACHE3_ACS_FAIL_ADDR (r) register accessor: L1-ICache0 Access Fail Address information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_acs_fail_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache3_acs_fail_addr`] module"]
2182pub type L1_ICACHE3_ACS_FAIL_ADDR =
2183 crate::Reg<l1_icache3_acs_fail_addr::L1_ICACHE3_ACS_FAIL_ADDR_SPEC>;
2184#[doc = "L1-ICache0 Access Fail Address information register"]
2185pub mod l1_icache3_acs_fail_addr;
2186#[doc = "L1_DCACHE_ACS_FAIL_ID_ATTR (r) register accessor: L1-DCache Access Fail ID/attribution information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_acs_fail_id_attr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_acs_fail_id_attr`] module"]
2187pub type L1_DCACHE_ACS_FAIL_ID_ATTR =
2188 crate::Reg<l1_dcache_acs_fail_id_attr::L1_DCACHE_ACS_FAIL_ID_ATTR_SPEC>;
2189#[doc = "L1-DCache Access Fail ID/attribution information register"]
2190pub mod l1_dcache_acs_fail_id_attr;
2191#[doc = "L1_DCACHE_ACS_FAIL_ADDR (r) register accessor: L1-DCache Access Fail Address information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_acs_fail_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_acs_fail_addr`] module"]
2192pub type L1_DCACHE_ACS_FAIL_ADDR =
2193 crate::Reg<l1_dcache_acs_fail_addr::L1_DCACHE_ACS_FAIL_ADDR_SPEC>;
2194#[doc = "L1-DCache Access Fail Address information register"]
2195pub mod l1_dcache_acs_fail_addr;
2196#[doc = "SYNC_L1_CACHE_PRELOAD_INT_ENA (rw) register accessor: L1-Cache Access Fail Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_l1_cache_preload_int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sync_l1_cache_preload_int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sync_l1_cache_preload_int_ena`] module"]
2197pub type SYNC_L1_CACHE_PRELOAD_INT_ENA =
2198 crate::Reg<sync_l1_cache_preload_int_ena::SYNC_L1_CACHE_PRELOAD_INT_ENA_SPEC>;
2199#[doc = "L1-Cache Access Fail Interrupt enable register"]
2200pub mod sync_l1_cache_preload_int_ena;
2201#[doc = "SYNC_L1_CACHE_PRELOAD_INT_CLR (rw) register accessor: Sync Preload operation Interrupt clear register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_l1_cache_preload_int_clr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sync_l1_cache_preload_int_clr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sync_l1_cache_preload_int_clr`] module"]
2202pub type SYNC_L1_CACHE_PRELOAD_INT_CLR =
2203 crate::Reg<sync_l1_cache_preload_int_clr::SYNC_L1_CACHE_PRELOAD_INT_CLR_SPEC>;
2204#[doc = "Sync Preload operation Interrupt clear register"]
2205pub mod sync_l1_cache_preload_int_clr;
2206#[doc = "SYNC_L1_CACHE_PRELOAD_INT_RAW (rw) register accessor: Sync Preload operation Interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_l1_cache_preload_int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sync_l1_cache_preload_int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sync_l1_cache_preload_int_raw`] module"]
2207pub type SYNC_L1_CACHE_PRELOAD_INT_RAW =
2208 crate::Reg<sync_l1_cache_preload_int_raw::SYNC_L1_CACHE_PRELOAD_INT_RAW_SPEC>;
2209#[doc = "Sync Preload operation Interrupt raw register"]
2210pub mod sync_l1_cache_preload_int_raw;
2211#[doc = "SYNC_L1_CACHE_PRELOAD_INT_ST (r) register accessor: L1-Cache Access Fail Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_l1_cache_preload_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sync_l1_cache_preload_int_st`] module"]
2212pub type SYNC_L1_CACHE_PRELOAD_INT_ST =
2213 crate::Reg<sync_l1_cache_preload_int_st::SYNC_L1_CACHE_PRELOAD_INT_ST_SPEC>;
2214#[doc = "L1-Cache Access Fail Interrupt status register"]
2215pub mod sync_l1_cache_preload_int_st;
2216#[doc = "SYNC_L1_CACHE_PRELOAD_EXCEPTION (r) register accessor: Cache Sync/Preload Operation exception register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_l1_cache_preload_exception::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sync_l1_cache_preload_exception`] module"]
2217pub type SYNC_L1_CACHE_PRELOAD_EXCEPTION =
2218 crate::Reg<sync_l1_cache_preload_exception::SYNC_L1_CACHE_PRELOAD_EXCEPTION_SPEC>;
2219#[doc = "Cache Sync/Preload Operation exception register"]
2220pub mod sync_l1_cache_preload_exception;
2221#[doc = "L1_CACHE_SYNC_RST_CTRL (rw) register accessor: Cache Sync Reset control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_sync_rst_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_sync_rst_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_sync_rst_ctrl`] module"]
2222pub type L1_CACHE_SYNC_RST_CTRL = crate::Reg<l1_cache_sync_rst_ctrl::L1_CACHE_SYNC_RST_CTRL_SPEC>;
2223#[doc = "Cache Sync Reset control register"]
2224pub mod l1_cache_sync_rst_ctrl;
2225#[doc = "L1_CACHE_PRELOAD_RST_CTRL (rw) register accessor: Cache Preload Reset control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_preload_rst_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_preload_rst_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_preload_rst_ctrl`] module"]
2226pub type L1_CACHE_PRELOAD_RST_CTRL =
2227 crate::Reg<l1_cache_preload_rst_ctrl::L1_CACHE_PRELOAD_RST_CTRL_SPEC>;
2228#[doc = "Cache Preload Reset control register"]
2229pub mod l1_cache_preload_rst_ctrl;
2230#[doc = "L1_CACHE_AUTOLOAD_BUF_CLR_CTRL (rw) register accessor: Cache Autoload buffer clear control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_autoload_buf_clr_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_autoload_buf_clr_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_autoload_buf_clr_ctrl`] module"]
2231pub type L1_CACHE_AUTOLOAD_BUF_CLR_CTRL =
2232 crate::Reg<l1_cache_autoload_buf_clr_ctrl::L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_SPEC>;
2233#[doc = "Cache Autoload buffer clear control register"]
2234pub mod l1_cache_autoload_buf_clr_ctrl;
2235#[doc = "L1_UNALLOCATE_BUFFER_CLEAR (rw) register accessor: Unallocate request buffer clear registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_unallocate_buffer_clear::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_unallocate_buffer_clear::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_unallocate_buffer_clear`] module"]
2236pub type L1_UNALLOCATE_BUFFER_CLEAR =
2237 crate::Reg<l1_unallocate_buffer_clear::L1_UNALLOCATE_BUFFER_CLEAR_SPEC>;
2238#[doc = "Unallocate request buffer clear registers"]
2239pub mod l1_unallocate_buffer_clear;
2240#[doc = "L1_CACHE_OBJECT_CTRL (rw) register accessor: Cache Tag and Data memory Object control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_object_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_object_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_object_ctrl`] module"]
2241pub type L1_CACHE_OBJECT_CTRL = crate::Reg<l1_cache_object_ctrl::L1_CACHE_OBJECT_CTRL_SPEC>;
2242#[doc = "Cache Tag and Data memory Object control register"]
2243pub mod l1_cache_object_ctrl;
2244#[doc = "L1_CACHE_WAY_OBJECT (rw) register accessor: Cache Tag and Data memory way register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_way_object::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_way_object::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_way_object`] module"]
2245pub type L1_CACHE_WAY_OBJECT = crate::Reg<l1_cache_way_object::L1_CACHE_WAY_OBJECT_SPEC>;
2246#[doc = "Cache Tag and Data memory way register"]
2247pub mod l1_cache_way_object;
2248#[doc = "L1_CACHE_VADDR (rw) register accessor: Cache Vaddr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_vaddr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_vaddr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_vaddr`] module"]
2249pub type L1_CACHE_VADDR = crate::Reg<l1_cache_vaddr::L1_CACHE_VADDR_SPEC>;
2250#[doc = "Cache Vaddr register"]
2251pub mod l1_cache_vaddr;
2252#[doc = "L1_CACHE_DEBUG_BUS (rw) register accessor: Cache Tag/data memory content register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_debug_bus::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_debug_bus::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_debug_bus`] module"]
2253pub type L1_CACHE_DEBUG_BUS = crate::Reg<l1_cache_debug_bus::L1_CACHE_DEBUG_BUS_SPEC>;
2254#[doc = "Cache Tag/data memory content register"]
2255pub mod l1_cache_debug_bus;
2256#[doc = "LEVEL_SPLIT0 (r) register accessor: USED TO SPLIT L1 CACHE AND L2 CACHE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`level_split0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@level_split0`] module"]
2257pub type LEVEL_SPLIT0 = crate::Reg<level_split0::LEVEL_SPLIT0_SPEC>;
2258#[doc = "USED TO SPLIT L1 CACHE AND L2 CACHE"]
2259pub mod level_split0;
2260#[doc = "L2_CACHE_CTRL (rw) register accessor: L2 Cache(L2-Cache) control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_ctrl`] module"]
2261pub type L2_CACHE_CTRL = crate::Reg<l2_cache_ctrl::L2_CACHE_CTRL_SPEC>;
2262#[doc = "L2 Cache(L2-Cache) control register"]
2263pub mod l2_cache_ctrl;
2264#[doc = "L2_BYPASS_CACHE_CONF (rw) register accessor: Bypass Cache configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_bypass_cache_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_bypass_cache_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_bypass_cache_conf`] module"]
2265pub type L2_BYPASS_CACHE_CONF = crate::Reg<l2_bypass_cache_conf::L2_BYPASS_CACHE_CONF_SPEC>;
2266#[doc = "Bypass Cache configure register"]
2267pub mod l2_bypass_cache_conf;
2268#[doc = "L2_CACHE_CACHESIZE_CONF (rw) register accessor: L2 Cache CacheSize mode configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_cachesize_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_cachesize_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_cachesize_conf`] module"]
2269pub type L2_CACHE_CACHESIZE_CONF =
2270 crate::Reg<l2_cache_cachesize_conf::L2_CACHE_CACHESIZE_CONF_SPEC>;
2271#[doc = "L2 Cache CacheSize mode configure register"]
2272pub mod l2_cache_cachesize_conf;
2273#[doc = "L2_CACHE_BLOCKSIZE_CONF (rw) register accessor: L2 Cache BlockSize mode configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_blocksize_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_blocksize_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_blocksize_conf`] module"]
2274pub type L2_CACHE_BLOCKSIZE_CONF =
2275 crate::Reg<l2_cache_blocksize_conf::L2_CACHE_BLOCKSIZE_CONF_SPEC>;
2276#[doc = "L2 Cache BlockSize mode configure register"]
2277pub mod l2_cache_blocksize_conf;
2278#[doc = "L2_CACHE_WRAP_AROUND_CTRL (rw) register accessor: Cache wrap around control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_wrap_around_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_wrap_around_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_wrap_around_ctrl`] module"]
2279pub type L2_CACHE_WRAP_AROUND_CTRL =
2280 crate::Reg<l2_cache_wrap_around_ctrl::L2_CACHE_WRAP_AROUND_CTRL_SPEC>;
2281#[doc = "Cache wrap around control register"]
2282pub mod l2_cache_wrap_around_ctrl;
2283#[doc = "L2_CACHE_TAG_MEM_POWER_CTRL (rw) register accessor: Cache tag memory power control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_tag_mem_power_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_tag_mem_power_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_tag_mem_power_ctrl`] module"]
2284pub type L2_CACHE_TAG_MEM_POWER_CTRL =
2285 crate::Reg<l2_cache_tag_mem_power_ctrl::L2_CACHE_TAG_MEM_POWER_CTRL_SPEC>;
2286#[doc = "Cache tag memory power control register"]
2287pub mod l2_cache_tag_mem_power_ctrl;
2288#[doc = "L2_CACHE_DATA_MEM_POWER_CTRL (rw) register accessor: Cache data memory power control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_data_mem_power_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_data_mem_power_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_data_mem_power_ctrl`] module"]
2289pub type L2_CACHE_DATA_MEM_POWER_CTRL =
2290 crate::Reg<l2_cache_data_mem_power_ctrl::L2_CACHE_DATA_MEM_POWER_CTRL_SPEC>;
2291#[doc = "Cache data memory power control register"]
2292pub mod l2_cache_data_mem_power_ctrl;
2293#[doc = "L2_CACHE_FREEZE_CTRL (rw) register accessor: Cache Freeze control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_freeze_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_freeze_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_freeze_ctrl`] module"]
2294pub type L2_CACHE_FREEZE_CTRL = crate::Reg<l2_cache_freeze_ctrl::L2_CACHE_FREEZE_CTRL_SPEC>;
2295#[doc = "Cache Freeze control register"]
2296pub mod l2_cache_freeze_ctrl;
2297#[doc = "L2_CACHE_DATA_MEM_ACS_CONF (rw) register accessor: Cache data memory access configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_data_mem_acs_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_data_mem_acs_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_data_mem_acs_conf`] module"]
2298pub type L2_CACHE_DATA_MEM_ACS_CONF =
2299 crate::Reg<l2_cache_data_mem_acs_conf::L2_CACHE_DATA_MEM_ACS_CONF_SPEC>;
2300#[doc = "Cache data memory access configure register"]
2301pub mod l2_cache_data_mem_acs_conf;
2302#[doc = "L2_CACHE_TAG_MEM_ACS_CONF (rw) register accessor: Cache tag memory access configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_tag_mem_acs_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_tag_mem_acs_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_tag_mem_acs_conf`] module"]
2303pub type L2_CACHE_TAG_MEM_ACS_CONF =
2304 crate::Reg<l2_cache_tag_mem_acs_conf::L2_CACHE_TAG_MEM_ACS_CONF_SPEC>;
2305#[doc = "Cache tag memory access configure register"]
2306pub mod l2_cache_tag_mem_acs_conf;
2307#[doc = "L2_CACHE_PRELOCK_CONF (rw) register accessor: L2 Cache prelock configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_prelock_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_prelock_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_prelock_conf`] module"]
2308pub type L2_CACHE_PRELOCK_CONF = crate::Reg<l2_cache_prelock_conf::L2_CACHE_PRELOCK_CONF_SPEC>;
2309#[doc = "L2 Cache prelock configure register"]
2310pub mod l2_cache_prelock_conf;
2311#[doc = "L2_CACHE_PRELOCK_SCT0_ADDR (rw) register accessor: L2 Cache prelock section0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_prelock_sct0_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_prelock_sct0_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_prelock_sct0_addr`] module"]
2312pub type L2_CACHE_PRELOCK_SCT0_ADDR =
2313 crate::Reg<l2_cache_prelock_sct0_addr::L2_CACHE_PRELOCK_SCT0_ADDR_SPEC>;
2314#[doc = "L2 Cache prelock section0 address configure register"]
2315pub mod l2_cache_prelock_sct0_addr;
2316#[doc = "L2_CACHE_PRELOCK_SCT1_ADDR (rw) register accessor: L2 Cache prelock section1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_prelock_sct1_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_prelock_sct1_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_prelock_sct1_addr`] module"]
2317pub type L2_CACHE_PRELOCK_SCT1_ADDR =
2318 crate::Reg<l2_cache_prelock_sct1_addr::L2_CACHE_PRELOCK_SCT1_ADDR_SPEC>;
2319#[doc = "L2 Cache prelock section1 address configure register"]
2320pub mod l2_cache_prelock_sct1_addr;
2321#[doc = "L2_CACHE_PRELOCK_SCT_SIZE (rw) register accessor: L2 Cache prelock section size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_prelock_sct_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_prelock_sct_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_prelock_sct_size`] module"]
2322pub type L2_CACHE_PRELOCK_SCT_SIZE =
2323 crate::Reg<l2_cache_prelock_sct_size::L2_CACHE_PRELOCK_SCT_SIZE_SPEC>;
2324#[doc = "L2 Cache prelock section size configure register"]
2325pub mod l2_cache_prelock_sct_size;
2326#[doc = "L2_CACHE_PRELOAD_CTRL (rw) register accessor: L2 Cache preload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_preload_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_preload_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_preload_ctrl`] module"]
2327pub type L2_CACHE_PRELOAD_CTRL = crate::Reg<l2_cache_preload_ctrl::L2_CACHE_PRELOAD_CTRL_SPEC>;
2328#[doc = "L2 Cache preload-operation control register"]
2329pub mod l2_cache_preload_ctrl;
2330#[doc = "L2_CACHE_PRELOAD_ADDR (rw) register accessor: L2 Cache preload address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_preload_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_preload_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_preload_addr`] module"]
2331pub type L2_CACHE_PRELOAD_ADDR = crate::Reg<l2_cache_preload_addr::L2_CACHE_PRELOAD_ADDR_SPEC>;
2332#[doc = "L2 Cache preload address configure register"]
2333pub mod l2_cache_preload_addr;
2334#[doc = "L2_CACHE_PRELOAD_SIZE (rw) register accessor: L2 Cache preload size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_preload_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_preload_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_preload_size`] module"]
2335pub type L2_CACHE_PRELOAD_SIZE = crate::Reg<l2_cache_preload_size::L2_CACHE_PRELOAD_SIZE_SPEC>;
2336#[doc = "L2 Cache preload size configure register"]
2337pub mod l2_cache_preload_size;
2338#[doc = "L2_CACHE_AUTOLOAD_CTRL (rw) register accessor: L2 Cache autoload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_autoload_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_autoload_ctrl`] module"]
2339pub type L2_CACHE_AUTOLOAD_CTRL = crate::Reg<l2_cache_autoload_ctrl::L2_CACHE_AUTOLOAD_CTRL_SPEC>;
2340#[doc = "L2 Cache autoload-operation control register"]
2341pub mod l2_cache_autoload_ctrl;
2342#[doc = "L2_CACHE_AUTOLOAD_SCT0_ADDR (rw) register accessor: L2 Cache autoload section 0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_sct0_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_autoload_sct0_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_autoload_sct0_addr`] module"]
2343pub type L2_CACHE_AUTOLOAD_SCT0_ADDR =
2344 crate::Reg<l2_cache_autoload_sct0_addr::L2_CACHE_AUTOLOAD_SCT0_ADDR_SPEC>;
2345#[doc = "L2 Cache autoload section 0 address configure register"]
2346pub mod l2_cache_autoload_sct0_addr;
2347#[doc = "L2_CACHE_AUTOLOAD_SCT0_SIZE (rw) register accessor: L2 Cache autoload section 0 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_sct0_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_autoload_sct0_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_autoload_sct0_size`] module"]
2348pub type L2_CACHE_AUTOLOAD_SCT0_SIZE =
2349 crate::Reg<l2_cache_autoload_sct0_size::L2_CACHE_AUTOLOAD_SCT0_SIZE_SPEC>;
2350#[doc = "L2 Cache autoload section 0 size configure register"]
2351pub mod l2_cache_autoload_sct0_size;
2352#[doc = "L2_CACHE_AUTOLOAD_SCT1_ADDR (rw) register accessor: L2 Cache autoload section 1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_sct1_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_autoload_sct1_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_autoload_sct1_addr`] module"]
2353pub type L2_CACHE_AUTOLOAD_SCT1_ADDR =
2354 crate::Reg<l2_cache_autoload_sct1_addr::L2_CACHE_AUTOLOAD_SCT1_ADDR_SPEC>;
2355#[doc = "L2 Cache autoload section 1 address configure register"]
2356pub mod l2_cache_autoload_sct1_addr;
2357#[doc = "L2_CACHE_AUTOLOAD_SCT1_SIZE (rw) register accessor: L2 Cache autoload section 1 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_sct1_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_autoload_sct1_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_autoload_sct1_size`] module"]
2358pub type L2_CACHE_AUTOLOAD_SCT1_SIZE =
2359 crate::Reg<l2_cache_autoload_sct1_size::L2_CACHE_AUTOLOAD_SCT1_SIZE_SPEC>;
2360#[doc = "L2 Cache autoload section 1 size configure register"]
2361pub mod l2_cache_autoload_sct1_size;
2362#[doc = "L2_CACHE_AUTOLOAD_SCT2_ADDR (rw) register accessor: L2 Cache autoload section 2 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_sct2_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_autoload_sct2_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_autoload_sct2_addr`] module"]
2363pub type L2_CACHE_AUTOLOAD_SCT2_ADDR =
2364 crate::Reg<l2_cache_autoload_sct2_addr::L2_CACHE_AUTOLOAD_SCT2_ADDR_SPEC>;
2365#[doc = "L2 Cache autoload section 2 address configure register"]
2366pub mod l2_cache_autoload_sct2_addr;
2367#[doc = "L2_CACHE_AUTOLOAD_SCT2_SIZE (rw) register accessor: L2 Cache autoload section 2 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_sct2_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_autoload_sct2_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_autoload_sct2_size`] module"]
2368pub type L2_CACHE_AUTOLOAD_SCT2_SIZE =
2369 crate::Reg<l2_cache_autoload_sct2_size::L2_CACHE_AUTOLOAD_SCT2_SIZE_SPEC>;
2370#[doc = "L2 Cache autoload section 2 size configure register"]
2371pub mod l2_cache_autoload_sct2_size;
2372#[doc = "L2_CACHE_AUTOLOAD_SCT3_ADDR (rw) register accessor: L2 Cache autoload section 3 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_sct3_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_autoload_sct3_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_autoload_sct3_addr`] module"]
2373pub type L2_CACHE_AUTOLOAD_SCT3_ADDR =
2374 crate::Reg<l2_cache_autoload_sct3_addr::L2_CACHE_AUTOLOAD_SCT3_ADDR_SPEC>;
2375#[doc = "L2 Cache autoload section 3 address configure register"]
2376pub mod l2_cache_autoload_sct3_addr;
2377#[doc = "L2_CACHE_AUTOLOAD_SCT3_SIZE (rw) register accessor: L2 Cache autoload section 3 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_sct3_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_autoload_sct3_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_autoload_sct3_size`] module"]
2378pub type L2_CACHE_AUTOLOAD_SCT3_SIZE =
2379 crate::Reg<l2_cache_autoload_sct3_size::L2_CACHE_AUTOLOAD_SCT3_SIZE_SPEC>;
2380#[doc = "L2 Cache autoload section 3 size configure register"]
2381pub mod l2_cache_autoload_sct3_size;
2382#[doc = "L2_CACHE_ACS_CNT_INT_ENA (rw) register accessor: Cache Access Counter Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_cnt_int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_acs_cnt_int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_acs_cnt_int_ena`] module"]
2383pub type L2_CACHE_ACS_CNT_INT_ENA =
2384 crate::Reg<l2_cache_acs_cnt_int_ena::L2_CACHE_ACS_CNT_INT_ENA_SPEC>;
2385#[doc = "Cache Access Counter Interrupt enable register"]
2386pub mod l2_cache_acs_cnt_int_ena;
2387#[doc = "L2_CACHE_ACS_CNT_INT_CLR (rw) register accessor: Cache Access Counter Interrupt clear register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_cnt_int_clr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_acs_cnt_int_clr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_acs_cnt_int_clr`] module"]
2388pub type L2_CACHE_ACS_CNT_INT_CLR =
2389 crate::Reg<l2_cache_acs_cnt_int_clr::L2_CACHE_ACS_CNT_INT_CLR_SPEC>;
2390#[doc = "Cache Access Counter Interrupt clear register"]
2391pub mod l2_cache_acs_cnt_int_clr;
2392#[doc = "L2_CACHE_ACS_CNT_INT_RAW (rw) register accessor: Cache Access Counter Interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_cnt_int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_acs_cnt_int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_acs_cnt_int_raw`] module"]
2393pub type L2_CACHE_ACS_CNT_INT_RAW =
2394 crate::Reg<l2_cache_acs_cnt_int_raw::L2_CACHE_ACS_CNT_INT_RAW_SPEC>;
2395#[doc = "Cache Access Counter Interrupt raw register"]
2396pub mod l2_cache_acs_cnt_int_raw;
2397#[doc = "L2_CACHE_ACS_CNT_INT_ST (r) register accessor: Cache Access Counter Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_cnt_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_acs_cnt_int_st`] module"]
2398pub type L2_CACHE_ACS_CNT_INT_ST =
2399 crate::Reg<l2_cache_acs_cnt_int_st::L2_CACHE_ACS_CNT_INT_ST_SPEC>;
2400#[doc = "Cache Access Counter Interrupt status register"]
2401pub mod l2_cache_acs_cnt_int_st;
2402#[doc = "L2_CACHE_ACS_FAIL_CTRL (rw) register accessor: Cache Access Fail Configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_fail_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_acs_fail_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_acs_fail_ctrl`] module"]
2403pub type L2_CACHE_ACS_FAIL_CTRL = crate::Reg<l2_cache_acs_fail_ctrl::L2_CACHE_ACS_FAIL_CTRL_SPEC>;
2404#[doc = "Cache Access Fail Configuration register"]
2405pub mod l2_cache_acs_fail_ctrl;
2406#[doc = "L2_CACHE_ACS_FAIL_INT_ENA (rw) register accessor: Cache Access Fail Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_fail_int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_acs_fail_int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_acs_fail_int_ena`] module"]
2407pub type L2_CACHE_ACS_FAIL_INT_ENA =
2408 crate::Reg<l2_cache_acs_fail_int_ena::L2_CACHE_ACS_FAIL_INT_ENA_SPEC>;
2409#[doc = "Cache Access Fail Interrupt enable register"]
2410pub mod l2_cache_acs_fail_int_ena;
2411#[doc = "L2_CACHE_ACS_FAIL_INT_CLR (w) register accessor: L1-Cache Access Fail Interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_acs_fail_int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_acs_fail_int_clr`] module"]
2412pub type L2_CACHE_ACS_FAIL_INT_CLR =
2413 crate::Reg<l2_cache_acs_fail_int_clr::L2_CACHE_ACS_FAIL_INT_CLR_SPEC>;
2414#[doc = "L1-Cache Access Fail Interrupt clear register"]
2415pub mod l2_cache_acs_fail_int_clr;
2416#[doc = "L2_CACHE_ACS_FAIL_INT_RAW (rw) register accessor: Cache Access Fail Interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_fail_int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_acs_fail_int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_acs_fail_int_raw`] module"]
2417pub type L2_CACHE_ACS_FAIL_INT_RAW =
2418 crate::Reg<l2_cache_acs_fail_int_raw::L2_CACHE_ACS_FAIL_INT_RAW_SPEC>;
2419#[doc = "Cache Access Fail Interrupt raw register"]
2420pub mod l2_cache_acs_fail_int_raw;
2421#[doc = "L2_CACHE_ACS_FAIL_INT_ST (r) register accessor: Cache Access Fail Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_fail_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_acs_fail_int_st`] module"]
2422pub type L2_CACHE_ACS_FAIL_INT_ST =
2423 crate::Reg<l2_cache_acs_fail_int_st::L2_CACHE_ACS_FAIL_INT_ST_SPEC>;
2424#[doc = "Cache Access Fail Interrupt status register"]
2425pub mod l2_cache_acs_fail_int_st;
2426#[doc = "L2_CACHE_ACS_CNT_CTRL (rw) register accessor: Cache Access Counter enable and clear register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_cnt_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_acs_cnt_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_acs_cnt_ctrl`] module"]
2427pub type L2_CACHE_ACS_CNT_CTRL = crate::Reg<l2_cache_acs_cnt_ctrl::L2_CACHE_ACS_CNT_CTRL_SPEC>;
2428#[doc = "Cache Access Counter enable and clear register"]
2429pub mod l2_cache_acs_cnt_ctrl;
2430#[doc = "L2_IBUS0_ACS_HIT_CNT (r) register accessor: L2-Cache bus0 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus0_acs_hit_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_ibus0_acs_hit_cnt`] module"]
2431pub type L2_IBUS0_ACS_HIT_CNT = crate::Reg<l2_ibus0_acs_hit_cnt::L2_IBUS0_ACS_HIT_CNT_SPEC>;
2432#[doc = "L2-Cache bus0 Hit-Access Counter register"]
2433pub mod l2_ibus0_acs_hit_cnt;
2434#[doc = "L2_IBUS0_ACS_MISS_CNT (r) register accessor: L2-Cache bus0 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus0_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_ibus0_acs_miss_cnt`] module"]
2435pub type L2_IBUS0_ACS_MISS_CNT = crate::Reg<l2_ibus0_acs_miss_cnt::L2_IBUS0_ACS_MISS_CNT_SPEC>;
2436#[doc = "L2-Cache bus0 Miss-Access Counter register"]
2437pub mod l2_ibus0_acs_miss_cnt;
2438#[doc = "L2_IBUS0_ACS_CONFLICT_CNT (r) register accessor: L2-Cache bus0 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus0_acs_conflict_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_ibus0_acs_conflict_cnt`] module"]
2439pub type L2_IBUS0_ACS_CONFLICT_CNT =
2440 crate::Reg<l2_ibus0_acs_conflict_cnt::L2_IBUS0_ACS_CONFLICT_CNT_SPEC>;
2441#[doc = "L2-Cache bus0 Conflict-Access Counter register"]
2442pub mod l2_ibus0_acs_conflict_cnt;
2443#[doc = "L2_IBUS0_ACS_NXTLVL_RD_CNT (r) register accessor: L2-Cache bus0 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus0_acs_nxtlvl_rd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_ibus0_acs_nxtlvl_rd_cnt`] module"]
2444pub type L2_IBUS0_ACS_NXTLVL_RD_CNT =
2445 crate::Reg<l2_ibus0_acs_nxtlvl_rd_cnt::L2_IBUS0_ACS_NXTLVL_RD_CNT_SPEC>;
2446#[doc = "L2-Cache bus0 Next-Level-Access Counter register"]
2447pub mod l2_ibus0_acs_nxtlvl_rd_cnt;
2448#[doc = "L2_IBUS1_ACS_HIT_CNT (r) register accessor: L2-Cache bus1 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus1_acs_hit_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_ibus1_acs_hit_cnt`] module"]
2449pub type L2_IBUS1_ACS_HIT_CNT = crate::Reg<l2_ibus1_acs_hit_cnt::L2_IBUS1_ACS_HIT_CNT_SPEC>;
2450#[doc = "L2-Cache bus1 Hit-Access Counter register"]
2451pub mod l2_ibus1_acs_hit_cnt;
2452#[doc = "L2_IBUS1_ACS_MISS_CNT (r) register accessor: L2-Cache bus1 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus1_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_ibus1_acs_miss_cnt`] module"]
2453pub type L2_IBUS1_ACS_MISS_CNT = crate::Reg<l2_ibus1_acs_miss_cnt::L2_IBUS1_ACS_MISS_CNT_SPEC>;
2454#[doc = "L2-Cache bus1 Miss-Access Counter register"]
2455pub mod l2_ibus1_acs_miss_cnt;
2456#[doc = "L2_IBUS1_ACS_CONFLICT_CNT (r) register accessor: L2-Cache bus1 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus1_acs_conflict_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_ibus1_acs_conflict_cnt`] module"]
2457pub type L2_IBUS1_ACS_CONFLICT_CNT =
2458 crate::Reg<l2_ibus1_acs_conflict_cnt::L2_IBUS1_ACS_CONFLICT_CNT_SPEC>;
2459#[doc = "L2-Cache bus1 Conflict-Access Counter register"]
2460pub mod l2_ibus1_acs_conflict_cnt;
2461#[doc = "L2_IBUS1_ACS_NXTLVL_RD_CNT (r) register accessor: L2-Cache bus1 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus1_acs_nxtlvl_rd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_ibus1_acs_nxtlvl_rd_cnt`] module"]
2462pub type L2_IBUS1_ACS_NXTLVL_RD_CNT =
2463 crate::Reg<l2_ibus1_acs_nxtlvl_rd_cnt::L2_IBUS1_ACS_NXTLVL_RD_CNT_SPEC>;
2464#[doc = "L2-Cache bus1 Next-Level-Access Counter register"]
2465pub mod l2_ibus1_acs_nxtlvl_rd_cnt;
2466#[doc = "L2_IBUS2_ACS_HIT_CNT (r) register accessor: L2-Cache bus2 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus2_acs_hit_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_ibus2_acs_hit_cnt`] module"]
2467pub type L2_IBUS2_ACS_HIT_CNT = crate::Reg<l2_ibus2_acs_hit_cnt::L2_IBUS2_ACS_HIT_CNT_SPEC>;
2468#[doc = "L2-Cache bus2 Hit-Access Counter register"]
2469pub mod l2_ibus2_acs_hit_cnt;
2470#[doc = "L2_IBUS2_ACS_MISS_CNT (r) register accessor: L2-Cache bus2 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus2_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_ibus2_acs_miss_cnt`] module"]
2471pub type L2_IBUS2_ACS_MISS_CNT = crate::Reg<l2_ibus2_acs_miss_cnt::L2_IBUS2_ACS_MISS_CNT_SPEC>;
2472#[doc = "L2-Cache bus2 Miss-Access Counter register"]
2473pub mod l2_ibus2_acs_miss_cnt;
2474#[doc = "L2_IBUS2_ACS_CONFLICT_CNT (r) register accessor: L2-Cache bus2 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus2_acs_conflict_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_ibus2_acs_conflict_cnt`] module"]
2475pub type L2_IBUS2_ACS_CONFLICT_CNT =
2476 crate::Reg<l2_ibus2_acs_conflict_cnt::L2_IBUS2_ACS_CONFLICT_CNT_SPEC>;
2477#[doc = "L2-Cache bus2 Conflict-Access Counter register"]
2478pub mod l2_ibus2_acs_conflict_cnt;
2479#[doc = "L2_IBUS2_ACS_NXTLVL_RD_CNT (r) register accessor: L2-Cache bus2 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus2_acs_nxtlvl_rd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_ibus2_acs_nxtlvl_rd_cnt`] module"]
2480pub type L2_IBUS2_ACS_NXTLVL_RD_CNT =
2481 crate::Reg<l2_ibus2_acs_nxtlvl_rd_cnt::L2_IBUS2_ACS_NXTLVL_RD_CNT_SPEC>;
2482#[doc = "L2-Cache bus2 Next-Level-Access Counter register"]
2483pub mod l2_ibus2_acs_nxtlvl_rd_cnt;
2484#[doc = "L2_IBUS3_ACS_HIT_CNT (r) register accessor: L2-Cache bus3 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus3_acs_hit_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_ibus3_acs_hit_cnt`] module"]
2485pub type L2_IBUS3_ACS_HIT_CNT = crate::Reg<l2_ibus3_acs_hit_cnt::L2_IBUS3_ACS_HIT_CNT_SPEC>;
2486#[doc = "L2-Cache bus3 Hit-Access Counter register"]
2487pub mod l2_ibus3_acs_hit_cnt;
2488#[doc = "L2_IBUS3_ACS_MISS_CNT (r) register accessor: L2-Cache bus3 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus3_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_ibus3_acs_miss_cnt`] module"]
2489pub type L2_IBUS3_ACS_MISS_CNT = crate::Reg<l2_ibus3_acs_miss_cnt::L2_IBUS3_ACS_MISS_CNT_SPEC>;
2490#[doc = "L2-Cache bus3 Miss-Access Counter register"]
2491pub mod l2_ibus3_acs_miss_cnt;
2492#[doc = "L2_IBUS3_ACS_CONFLICT_CNT (r) register accessor: L2-Cache bus3 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus3_acs_conflict_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_ibus3_acs_conflict_cnt`] module"]
2493pub type L2_IBUS3_ACS_CONFLICT_CNT =
2494 crate::Reg<l2_ibus3_acs_conflict_cnt::L2_IBUS3_ACS_CONFLICT_CNT_SPEC>;
2495#[doc = "L2-Cache bus3 Conflict-Access Counter register"]
2496pub mod l2_ibus3_acs_conflict_cnt;
2497#[doc = "L2_IBUS3_ACS_NXTLVL_RD_CNT (r) register accessor: L2-Cache bus3 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus3_acs_nxtlvl_rd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_ibus3_acs_nxtlvl_rd_cnt`] module"]
2498pub type L2_IBUS3_ACS_NXTLVL_RD_CNT =
2499 crate::Reg<l2_ibus3_acs_nxtlvl_rd_cnt::L2_IBUS3_ACS_NXTLVL_RD_CNT_SPEC>;
2500#[doc = "L2-Cache bus3 Next-Level-Access Counter register"]
2501pub mod l2_ibus3_acs_nxtlvl_rd_cnt;
2502#[doc = "L2_DBUS0_ACS_HIT_CNT (r) register accessor: L2-Cache bus0 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus0_acs_hit_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus0_acs_hit_cnt`] module"]
2503pub type L2_DBUS0_ACS_HIT_CNT = crate::Reg<l2_dbus0_acs_hit_cnt::L2_DBUS0_ACS_HIT_CNT_SPEC>;
2504#[doc = "L2-Cache bus0 Hit-Access Counter register"]
2505pub mod l2_dbus0_acs_hit_cnt;
2506#[doc = "L2_DBUS0_ACS_MISS_CNT (r) register accessor: L2-Cache bus0 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus0_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus0_acs_miss_cnt`] module"]
2507pub type L2_DBUS0_ACS_MISS_CNT = crate::Reg<l2_dbus0_acs_miss_cnt::L2_DBUS0_ACS_MISS_CNT_SPEC>;
2508#[doc = "L2-Cache bus0 Miss-Access Counter register"]
2509pub mod l2_dbus0_acs_miss_cnt;
2510#[doc = "L2_DBUS0_ACS_CONFLICT_CNT (r) register accessor: L2-Cache bus0 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus0_acs_conflict_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus0_acs_conflict_cnt`] module"]
2511pub type L2_DBUS0_ACS_CONFLICT_CNT =
2512 crate::Reg<l2_dbus0_acs_conflict_cnt::L2_DBUS0_ACS_CONFLICT_CNT_SPEC>;
2513#[doc = "L2-Cache bus0 Conflict-Access Counter register"]
2514pub mod l2_dbus0_acs_conflict_cnt;
2515#[doc = "L2_DBUS0_ACS_NXTLVL_RD_CNT (r) register accessor: L2-Cache bus0 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus0_acs_nxtlvl_rd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus0_acs_nxtlvl_rd_cnt`] module"]
2516pub type L2_DBUS0_ACS_NXTLVL_RD_CNT =
2517 crate::Reg<l2_dbus0_acs_nxtlvl_rd_cnt::L2_DBUS0_ACS_NXTLVL_RD_CNT_SPEC>;
2518#[doc = "L2-Cache bus0 Next-Level-Access Counter register"]
2519pub mod l2_dbus0_acs_nxtlvl_rd_cnt;
2520#[doc = "L2_DBUS0_ACS_NXTLVL_WR_CNT (r) register accessor: L2-Cache bus0 WB-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus0_acs_nxtlvl_wr_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus0_acs_nxtlvl_wr_cnt`] module"]
2521pub type L2_DBUS0_ACS_NXTLVL_WR_CNT =
2522 crate::Reg<l2_dbus0_acs_nxtlvl_wr_cnt::L2_DBUS0_ACS_NXTLVL_WR_CNT_SPEC>;
2523#[doc = "L2-Cache bus0 WB-Access Counter register"]
2524pub mod l2_dbus0_acs_nxtlvl_wr_cnt;
2525#[doc = "L2_DBUS1_ACS_HIT_CNT (r) register accessor: L2-Cache bus1 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus1_acs_hit_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus1_acs_hit_cnt`] module"]
2526pub type L2_DBUS1_ACS_HIT_CNT = crate::Reg<l2_dbus1_acs_hit_cnt::L2_DBUS1_ACS_HIT_CNT_SPEC>;
2527#[doc = "L2-Cache bus1 Hit-Access Counter register"]
2528pub mod l2_dbus1_acs_hit_cnt;
2529#[doc = "L2_DBUS1_ACS_MISS_CNT (r) register accessor: L2-Cache bus1 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus1_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus1_acs_miss_cnt`] module"]
2530pub type L2_DBUS1_ACS_MISS_CNT = crate::Reg<l2_dbus1_acs_miss_cnt::L2_DBUS1_ACS_MISS_CNT_SPEC>;
2531#[doc = "L2-Cache bus1 Miss-Access Counter register"]
2532pub mod l2_dbus1_acs_miss_cnt;
2533#[doc = "L2_DBUS1_ACS_CONFLICT_CNT (r) register accessor: L2-Cache bus1 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus1_acs_conflict_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus1_acs_conflict_cnt`] module"]
2534pub type L2_DBUS1_ACS_CONFLICT_CNT =
2535 crate::Reg<l2_dbus1_acs_conflict_cnt::L2_DBUS1_ACS_CONFLICT_CNT_SPEC>;
2536#[doc = "L2-Cache bus1 Conflict-Access Counter register"]
2537pub mod l2_dbus1_acs_conflict_cnt;
2538#[doc = "L2_DBUS1_ACS_NXTLVL_RD_CNT (r) register accessor: L2-Cache bus1 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus1_acs_nxtlvl_rd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus1_acs_nxtlvl_rd_cnt`] module"]
2539pub type L2_DBUS1_ACS_NXTLVL_RD_CNT =
2540 crate::Reg<l2_dbus1_acs_nxtlvl_rd_cnt::L2_DBUS1_ACS_NXTLVL_RD_CNT_SPEC>;
2541#[doc = "L2-Cache bus1 Next-Level-Access Counter register"]
2542pub mod l2_dbus1_acs_nxtlvl_rd_cnt;
2543#[doc = "L2_DBUS1_ACS_NXTLVL_WR_CNT (r) register accessor: L2-Cache bus1 WB-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus1_acs_nxtlvl_wr_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus1_acs_nxtlvl_wr_cnt`] module"]
2544pub type L2_DBUS1_ACS_NXTLVL_WR_CNT =
2545 crate::Reg<l2_dbus1_acs_nxtlvl_wr_cnt::L2_DBUS1_ACS_NXTLVL_WR_CNT_SPEC>;
2546#[doc = "L2-Cache bus1 WB-Access Counter register"]
2547pub mod l2_dbus1_acs_nxtlvl_wr_cnt;
2548#[doc = "L2_DBUS2_ACS_HIT_CNT (r) register accessor: L2-Cache bus2 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus2_acs_hit_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus2_acs_hit_cnt`] module"]
2549pub type L2_DBUS2_ACS_HIT_CNT = crate::Reg<l2_dbus2_acs_hit_cnt::L2_DBUS2_ACS_HIT_CNT_SPEC>;
2550#[doc = "L2-Cache bus2 Hit-Access Counter register"]
2551pub mod l2_dbus2_acs_hit_cnt;
2552#[doc = "L2_DBUS2_ACS_MISS_CNT (r) register accessor: L2-Cache bus2 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus2_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus2_acs_miss_cnt`] module"]
2553pub type L2_DBUS2_ACS_MISS_CNT = crate::Reg<l2_dbus2_acs_miss_cnt::L2_DBUS2_ACS_MISS_CNT_SPEC>;
2554#[doc = "L2-Cache bus2 Miss-Access Counter register"]
2555pub mod l2_dbus2_acs_miss_cnt;
2556#[doc = "L2_DBUS2_ACS_CONFLICT_CNT (r) register accessor: L2-Cache bus2 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus2_acs_conflict_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus2_acs_conflict_cnt`] module"]
2557pub type L2_DBUS2_ACS_CONFLICT_CNT =
2558 crate::Reg<l2_dbus2_acs_conflict_cnt::L2_DBUS2_ACS_CONFLICT_CNT_SPEC>;
2559#[doc = "L2-Cache bus2 Conflict-Access Counter register"]
2560pub mod l2_dbus2_acs_conflict_cnt;
2561#[doc = "L2_DBUS2_ACS_NXTLVL_RD_CNT (r) register accessor: L2-Cache bus2 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus2_acs_nxtlvl_rd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus2_acs_nxtlvl_rd_cnt`] module"]
2562pub type L2_DBUS2_ACS_NXTLVL_RD_CNT =
2563 crate::Reg<l2_dbus2_acs_nxtlvl_rd_cnt::L2_DBUS2_ACS_NXTLVL_RD_CNT_SPEC>;
2564#[doc = "L2-Cache bus2 Next-Level-Access Counter register"]
2565pub mod l2_dbus2_acs_nxtlvl_rd_cnt;
2566#[doc = "L2_DBUS2_ACS_NXTLVL_WR_CNT (r) register accessor: L2-Cache bus2 WB-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus2_acs_nxtlvl_wr_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus2_acs_nxtlvl_wr_cnt`] module"]
2567pub type L2_DBUS2_ACS_NXTLVL_WR_CNT =
2568 crate::Reg<l2_dbus2_acs_nxtlvl_wr_cnt::L2_DBUS2_ACS_NXTLVL_WR_CNT_SPEC>;
2569#[doc = "L2-Cache bus2 WB-Access Counter register"]
2570pub mod l2_dbus2_acs_nxtlvl_wr_cnt;
2571#[doc = "L2_DBUS3_ACS_HIT_CNT (r) register accessor: L2-Cache bus3 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus3_acs_hit_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus3_acs_hit_cnt`] module"]
2572pub type L2_DBUS3_ACS_HIT_CNT = crate::Reg<l2_dbus3_acs_hit_cnt::L2_DBUS3_ACS_HIT_CNT_SPEC>;
2573#[doc = "L2-Cache bus3 Hit-Access Counter register"]
2574pub mod l2_dbus3_acs_hit_cnt;
2575#[doc = "L2_DBUS3_ACS_MISS_CNT (r) register accessor: L2-Cache bus3 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus3_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus3_acs_miss_cnt`] module"]
2576pub type L2_DBUS3_ACS_MISS_CNT = crate::Reg<l2_dbus3_acs_miss_cnt::L2_DBUS3_ACS_MISS_CNT_SPEC>;
2577#[doc = "L2-Cache bus3 Miss-Access Counter register"]
2578pub mod l2_dbus3_acs_miss_cnt;
2579#[doc = "L2_DBUS3_ACS_CONFLICT_CNT (r) register accessor: L2-Cache bus3 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus3_acs_conflict_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus3_acs_conflict_cnt`] module"]
2580pub type L2_DBUS3_ACS_CONFLICT_CNT =
2581 crate::Reg<l2_dbus3_acs_conflict_cnt::L2_DBUS3_ACS_CONFLICT_CNT_SPEC>;
2582#[doc = "L2-Cache bus3 Conflict-Access Counter register"]
2583pub mod l2_dbus3_acs_conflict_cnt;
2584#[doc = "L2_DBUS3_ACS_NXTLVL_RD_CNT (r) register accessor: L2-Cache bus3 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus3_acs_nxtlvl_rd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus3_acs_nxtlvl_rd_cnt`] module"]
2585pub type L2_DBUS3_ACS_NXTLVL_RD_CNT =
2586 crate::Reg<l2_dbus3_acs_nxtlvl_rd_cnt::L2_DBUS3_ACS_NXTLVL_RD_CNT_SPEC>;
2587#[doc = "L2-Cache bus3 Next-Level-Access Counter register"]
2588pub mod l2_dbus3_acs_nxtlvl_rd_cnt;
2589#[doc = "L2_DBUS3_ACS_NXTLVL_WR_CNT (r) register accessor: L2-Cache bus3 WB-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus3_acs_nxtlvl_wr_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus3_acs_nxtlvl_wr_cnt`] module"]
2590pub type L2_DBUS3_ACS_NXTLVL_WR_CNT =
2591 crate::Reg<l2_dbus3_acs_nxtlvl_wr_cnt::L2_DBUS3_ACS_NXTLVL_WR_CNT_SPEC>;
2592#[doc = "L2-Cache bus3 WB-Access Counter register"]
2593pub mod l2_dbus3_acs_nxtlvl_wr_cnt;
2594#[doc = "L2_CACHE_ACS_FAIL_ID_ATTR (r) register accessor: L2-Cache Access Fail ID/attribution information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_fail_id_attr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_acs_fail_id_attr`] module"]
2595pub type L2_CACHE_ACS_FAIL_ID_ATTR =
2596 crate::Reg<l2_cache_acs_fail_id_attr::L2_CACHE_ACS_FAIL_ID_ATTR_SPEC>;
2597#[doc = "L2-Cache Access Fail ID/attribution information register"]
2598pub mod l2_cache_acs_fail_id_attr;
2599#[doc = "L2_CACHE_ACS_FAIL_ADDR (r) register accessor: L2-Cache Access Fail Address information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_fail_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_acs_fail_addr`] module"]
2600pub type L2_CACHE_ACS_FAIL_ADDR = crate::Reg<l2_cache_acs_fail_addr::L2_CACHE_ACS_FAIL_ADDR_SPEC>;
2601#[doc = "L2-Cache Access Fail Address information register"]
2602pub mod l2_cache_acs_fail_addr;
2603#[doc = "L2_CACHE_SYNC_PRELOAD_INT_ENA (rw) register accessor: L1-Cache Access Fail Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_sync_preload_int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_sync_preload_int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_sync_preload_int_ena`] module"]
2604pub type L2_CACHE_SYNC_PRELOAD_INT_ENA =
2605 crate::Reg<l2_cache_sync_preload_int_ena::L2_CACHE_SYNC_PRELOAD_INT_ENA_SPEC>;
2606#[doc = "L1-Cache Access Fail Interrupt enable register"]
2607pub mod l2_cache_sync_preload_int_ena;
2608#[doc = "L2_CACHE_SYNC_PRELOAD_INT_CLR (w) register accessor: Sync Preload operation Interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_sync_preload_int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_sync_preload_int_clr`] module"]
2609pub type L2_CACHE_SYNC_PRELOAD_INT_CLR =
2610 crate::Reg<l2_cache_sync_preload_int_clr::L2_CACHE_SYNC_PRELOAD_INT_CLR_SPEC>;
2611#[doc = "Sync Preload operation Interrupt clear register"]
2612pub mod l2_cache_sync_preload_int_clr;
2613#[doc = "L2_CACHE_SYNC_PRELOAD_INT_RAW (rw) register accessor: Sync Preload operation Interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_sync_preload_int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_sync_preload_int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_sync_preload_int_raw`] module"]
2614pub type L2_CACHE_SYNC_PRELOAD_INT_RAW =
2615 crate::Reg<l2_cache_sync_preload_int_raw::L2_CACHE_SYNC_PRELOAD_INT_RAW_SPEC>;
2616#[doc = "Sync Preload operation Interrupt raw register"]
2617pub mod l2_cache_sync_preload_int_raw;
2618#[doc = "L2_CACHE_SYNC_PRELOAD_INT_ST (r) register accessor: L1-Cache Access Fail Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_sync_preload_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_sync_preload_int_st`] module"]
2619pub type L2_CACHE_SYNC_PRELOAD_INT_ST =
2620 crate::Reg<l2_cache_sync_preload_int_st::L2_CACHE_SYNC_PRELOAD_INT_ST_SPEC>;
2621#[doc = "L1-Cache Access Fail Interrupt status register"]
2622pub mod l2_cache_sync_preload_int_st;
2623#[doc = "L2_CACHE_SYNC_PRELOAD_EXCEPTION (r) register accessor: Cache Sync/Preload Operation exception register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_sync_preload_exception::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_sync_preload_exception`] module"]
2624pub type L2_CACHE_SYNC_PRELOAD_EXCEPTION =
2625 crate::Reg<l2_cache_sync_preload_exception::L2_CACHE_SYNC_PRELOAD_EXCEPTION_SPEC>;
2626#[doc = "Cache Sync/Preload Operation exception register"]
2627pub mod l2_cache_sync_preload_exception;
2628#[doc = "L2_CACHE_SYNC_RST_CTRL (rw) register accessor: Cache Sync Reset control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_sync_rst_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_sync_rst_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_sync_rst_ctrl`] module"]
2629pub type L2_CACHE_SYNC_RST_CTRL = crate::Reg<l2_cache_sync_rst_ctrl::L2_CACHE_SYNC_RST_CTRL_SPEC>;
2630#[doc = "Cache Sync Reset control register"]
2631pub mod l2_cache_sync_rst_ctrl;
2632#[doc = "L2_CACHE_PRELOAD_RST_CTRL (rw) register accessor: Cache Preload Reset control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_preload_rst_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_preload_rst_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_preload_rst_ctrl`] module"]
2633pub type L2_CACHE_PRELOAD_RST_CTRL =
2634 crate::Reg<l2_cache_preload_rst_ctrl::L2_CACHE_PRELOAD_RST_CTRL_SPEC>;
2635#[doc = "Cache Preload Reset control register"]
2636pub mod l2_cache_preload_rst_ctrl;
2637#[doc = "L2_CACHE_AUTOLOAD_BUF_CLR_CTRL (rw) register accessor: Cache Autoload buffer clear control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_buf_clr_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_autoload_buf_clr_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_autoload_buf_clr_ctrl`] module"]
2638pub type L2_CACHE_AUTOLOAD_BUF_CLR_CTRL =
2639 crate::Reg<l2_cache_autoload_buf_clr_ctrl::L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_SPEC>;
2640#[doc = "Cache Autoload buffer clear control register"]
2641pub mod l2_cache_autoload_buf_clr_ctrl;
2642#[doc = "L2_UNALLOCATE_BUFFER_CLEAR (rw) register accessor: Unallocate request buffer clear registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_unallocate_buffer_clear::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_unallocate_buffer_clear::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_unallocate_buffer_clear`] module"]
2643pub type L2_UNALLOCATE_BUFFER_CLEAR =
2644 crate::Reg<l2_unallocate_buffer_clear::L2_UNALLOCATE_BUFFER_CLEAR_SPEC>;
2645#[doc = "Unallocate request buffer clear registers"]
2646pub mod l2_unallocate_buffer_clear;
2647#[doc = "L2_CACHE_ACCESS_ATTR_CTRL (rw) register accessor: L2 cache access attribute control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_access_attr_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_access_attr_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_access_attr_ctrl`] module"]
2648pub type L2_CACHE_ACCESS_ATTR_CTRL =
2649 crate::Reg<l2_cache_access_attr_ctrl::L2_CACHE_ACCESS_ATTR_CTRL_SPEC>;
2650#[doc = "L2 cache access attribute control register"]
2651pub mod l2_cache_access_attr_ctrl;
2652#[doc = "L2_CACHE_OBJECT_CTRL (rw) register accessor: Cache Tag and Data memory Object control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_object_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_object_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_object_ctrl`] module"]
2653pub type L2_CACHE_OBJECT_CTRL = crate::Reg<l2_cache_object_ctrl::L2_CACHE_OBJECT_CTRL_SPEC>;
2654#[doc = "Cache Tag and Data memory Object control register"]
2655pub mod l2_cache_object_ctrl;
2656#[doc = "L2_CACHE_WAY_OBJECT (rw) register accessor: Cache Tag and Data memory way register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_way_object::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_way_object::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_way_object`] module"]
2657pub type L2_CACHE_WAY_OBJECT = crate::Reg<l2_cache_way_object::L2_CACHE_WAY_OBJECT_SPEC>;
2658#[doc = "Cache Tag and Data memory way register"]
2659pub mod l2_cache_way_object;
2660#[doc = "L2_CACHE_VADDR (rw) register accessor: Cache Vaddr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_vaddr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_vaddr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_vaddr`] module"]
2661pub type L2_CACHE_VADDR = crate::Reg<l2_cache_vaddr::L2_CACHE_VADDR_SPEC>;
2662#[doc = "Cache Vaddr register"]
2663pub mod l2_cache_vaddr;
2664#[doc = "L2_CACHE_DEBUG_BUS (rw) register accessor: Cache Tag/data memory content register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_debug_bus::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_debug_bus::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_debug_bus`] module"]
2665pub type L2_CACHE_DEBUG_BUS = crate::Reg<l2_cache_debug_bus::L2_CACHE_DEBUG_BUS_SPEC>;
2666#[doc = "Cache Tag/data memory content register"]
2667pub mod l2_cache_debug_bus;
2668#[doc = "LEVEL_SPLIT1 (r) register accessor: USED TO SPLIT L1 CACHE AND L2 CACHE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`level_split1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@level_split1`] module"]
2669pub type LEVEL_SPLIT1 = crate::Reg<level_split1::LEVEL_SPLIT1_SPEC>;
2670#[doc = "USED TO SPLIT L1 CACHE AND L2 CACHE"]
2671pub mod level_split1;
2672#[doc = "CLOCK_GATE (rw) register accessor: Clock gate control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clock_gate::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clock_gate::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clock_gate`] module"]
2673pub type CLOCK_GATE = crate::Reg<clock_gate::CLOCK_GATE_SPEC>;
2674#[doc = "Clock gate control register"]
2675pub mod clock_gate;
2676#[doc = "REDUNDANCY_SIG0 (rw) register accessor: Cache redundancy signal 0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`redundancy_sig0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`redundancy_sig0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@redundancy_sig0`] module"]
2677pub type REDUNDANCY_SIG0 = crate::Reg<redundancy_sig0::REDUNDANCY_SIG0_SPEC>;
2678#[doc = "Cache redundancy signal 0 register"]
2679pub mod redundancy_sig0;
2680#[doc = "REDUNDANCY_SIG1 (rw) register accessor: Cache redundancy signal 1 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`redundancy_sig1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`redundancy_sig1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@redundancy_sig1`] module"]
2681pub type REDUNDANCY_SIG1 = crate::Reg<redundancy_sig1::REDUNDANCY_SIG1_SPEC>;
2682#[doc = "Cache redundancy signal 1 register"]
2683pub mod redundancy_sig1;
2684#[doc = "REDUNDANCY_SIG2 (rw) register accessor: Cache redundancy signal 2 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`redundancy_sig2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`redundancy_sig2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@redundancy_sig2`] module"]
2685pub type REDUNDANCY_SIG2 = crate::Reg<redundancy_sig2::REDUNDANCY_SIG2_SPEC>;
2686#[doc = "Cache redundancy signal 2 register"]
2687pub mod redundancy_sig2;
2688#[doc = "REDUNDANCY_SIG3 (rw) register accessor: Cache redundancy signal 3 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`redundancy_sig3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`redundancy_sig3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@redundancy_sig3`] module"]
2689pub type REDUNDANCY_SIG3 = crate::Reg<redundancy_sig3::REDUNDANCY_SIG3_SPEC>;
2690#[doc = "Cache redundancy signal 3 register"]
2691pub mod redundancy_sig3;
2692#[doc = "REDUNDANCY_SIG4 (r) register accessor: Cache redundancy signal 0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`redundancy_sig4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@redundancy_sig4`] module"]
2693pub type REDUNDANCY_SIG4 = crate::Reg<redundancy_sig4::REDUNDANCY_SIG4_SPEC>;
2694#[doc = "Cache redundancy signal 0 register"]
2695pub mod redundancy_sig4;
2696#[doc = "DATE (rw) register accessor: Version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"]
2697pub type DATE = crate::Reg<date::DATE_SPEC>;
2698#[doc = "Version control register"]
2699pub mod date;