Module ctrl2

SPI0 control2 register.

Structs

CTRL2_SPEC

SPI0 control2 register.

Type Aliases

CS_HOLD_DELAY_R

Field CS_HOLD_DELAY reader - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.

CS_HOLD_DELAY_W

Field CS_HOLD_DELAY writer - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.

CS_HOLD_TIME_R

Field CS_HOLD_TIME reader - SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit.

CS_HOLD_TIME_W

Field CS_HOLD_TIME writer - SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit.

CS_SETUP_TIME_R

Field CS_SETUP_TIME reader - (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit.

CS_SETUP_TIME_W

Field CS_SETUP_TIME writer - (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit.

ECC_16TO18_BYTE_EN_R

Field ECC_16TO18_BYTE_EN reader - Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash.

ECC_16TO18_BYTE_EN_W

Field ECC_16TO18_BYTE_EN writer - Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash.

ECC_CS_HOLD_TIME_R

Field ECC_CS_HOLD_TIME reader - SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash.

ECC_CS_HOLD_TIME_W

Field ECC_CS_HOLD_TIME writer - SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash.

ECC_SKIP_PAGE_CORNER_R

Field ECC_SKIP_PAGE_CORNER reader - 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash.

ECC_SKIP_PAGE_CORNER_W

Field ECC_SKIP_PAGE_CORNER writer - 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash.

R

Register CTRL2 reader

SPLIT_TRANS_EN_R

Field SPLIT_TRANS_EN reader - Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not.

SPLIT_TRANS_EN_W

Field SPLIT_TRANS_EN writer - Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not.

SYNC_RESET_W

Field SYNC_RESET writer - The spi0_mst_st and spi0_slv_st will be reset.

W

Register CTRL2 writer