esp32p4/cache/
l1_icache2_preload_size.rs

1#[doc = "Register `L1_ICACHE2_PRELOAD_SIZE` reader"]
2pub type R = crate::R<L1_ICACHE2_PRELOAD_SIZE_SPEC>;
3#[doc = "Field `L1_ICACHE2_PRELOAD_SIZE` reader - Those bits are used to configure the size of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG"]
4pub type L1_ICACHE2_PRELOAD_SIZE_R = crate::FieldReader<u16>;
5impl R {
6    #[doc = "Bits 0:13 - Those bits are used to configure the size of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG"]
7    #[inline(always)]
8    pub fn l1_icache2_preload_size(&self) -> L1_ICACHE2_PRELOAD_SIZE_R {
9        L1_ICACHE2_PRELOAD_SIZE_R::new((self.bits & 0x3fff) as u16)
10    }
11}
12#[cfg(feature = "impl-register-debug")]
13impl core::fmt::Debug for R {
14    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
15        f.debug_struct("L1_ICACHE2_PRELOAD_SIZE")
16            .field(
17                "l1_icache2_preload_size",
18                &format_args!("{}", self.l1_icache2_preload_size().bits()),
19            )
20            .finish()
21    }
22}
23#[cfg(feature = "impl-register-debug")]
24impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE2_PRELOAD_SIZE_SPEC> {
25    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
26        core::fmt::Debug::fmt(&self.read(), f)
27    }
28}
29#[doc = "L1 instruction Cache 2 preload size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_preload_size::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30pub struct L1_ICACHE2_PRELOAD_SIZE_SPEC;
31impl crate::RegisterSpec for L1_ICACHE2_PRELOAD_SIZE_SPEC {
32    type Ux = u32;
33}
34#[doc = "`read()` method returns [`l1_icache2_preload_size::R`](R) reader structure"]
35impl crate::Readable for L1_ICACHE2_PRELOAD_SIZE_SPEC {}
36#[doc = "`reset()` method sets L1_ICACHE2_PRELOAD_SIZE to value 0"]
37impl crate::Resettable for L1_ICACHE2_PRELOAD_SIZE_SPEC {
38    const RESET_VALUE: u32 = 0;
39}
esp32p4/cache/l1_icache2_preload_size.rs

esp32p4/cache/
l1_icache2_preload_size.rs
