1#[doc = "Register `INTERRUPT_ENABLE` reader"]
2pub type R = crate::R<INTERRUPT_ENABLE_SPEC>;
3#[doc = "Register `INTERRUPT_ENABLE` writer"]
4pub type W = crate::W<INTERRUPT_ENABLE_SPEC>;
5#[doc = "Field `EXT_RECEIVE_INT_ENA` reader - 1: enabled, when the receive buffer status is 'full' the TWAI controller requests the respective interrupt. 0: disable"]
6pub type EXT_RECEIVE_INT_ENA_R = crate::BitReader;
7#[doc = "Field `EXT_RECEIVE_INT_ENA` writer - 1: enabled, when the receive buffer status is 'full' the TWAI controller requests the respective interrupt. 0: disable"]
8pub type EXT_RECEIVE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `EXT_TRANSMIT_INT_ENA` reader - 1: enabled, when a message has been successfully transmitted or the transmit buffer is accessible again (e.g. after an abort transmission command), the TWAI controller requests the respective interrupt. 0: disable"]
10pub type EXT_TRANSMIT_INT_ENA_R = crate::BitReader;
11#[doc = "Field `EXT_TRANSMIT_INT_ENA` writer - 1: enabled, when a message has been successfully transmitted or the transmit buffer is accessible again (e.g. after an abort transmission command), the TWAI controller requests the respective interrupt. 0: disable"]
12pub type EXT_TRANSMIT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `EXT_ERR_WARNING_INT_ENA` reader - 1: enabled, if the error or bus status change (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable"]
14pub type EXT_ERR_WARNING_INT_ENA_R = crate::BitReader;
15#[doc = "Field `EXT_ERR_WARNING_INT_ENA` writer - 1: enabled, if the error or bus status change (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable"]
16pub type EXT_ERR_WARNING_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `EXT_DATA_OVERRUN_INT_ENA` reader - 1: enabled, if the data overrun status bit is set (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable"]
18pub type EXT_DATA_OVERRUN_INT_ENA_R = crate::BitReader;
19#[doc = "Field `EXT_DATA_OVERRUN_INT_ENA` writer - 1: enabled, if the data overrun status bit is set (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable"]
20pub type EXT_DATA_OVERRUN_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `TS_COUNTER_OVFL_INT_ENA` reader - enable the timestamp counter overflow interrupt request."]
22pub type TS_COUNTER_OVFL_INT_ENA_R = crate::BitReader;
23#[doc = "Field `TS_COUNTER_OVFL_INT_ENA` writer - enable the timestamp counter overflow interrupt request."]
24pub type TS_COUNTER_OVFL_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `ERR_PASSIVE_INT_ENA` reader - 1: enabled, if the error status of the TWAI controller changes from error active to error passive or vice versa, the respective interrupt is requested. 0: disable"]
26pub type ERR_PASSIVE_INT_ENA_R = crate::BitReader;
27#[doc = "Field `ERR_PASSIVE_INT_ENA` writer - 1: enabled, if the error status of the TWAI controller changes from error active to error passive or vice versa, the respective interrupt is requested. 0: disable"]
28pub type ERR_PASSIVE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `ARBITRATION_LOST_INT_ENA` reader - 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt is requested. 0: disable"]
30pub type ARBITRATION_LOST_INT_ENA_R = crate::BitReader;
31#[doc = "Field `ARBITRATION_LOST_INT_ENA` writer - 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt is requested. 0: disable"]
32pub type ARBITRATION_LOST_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `BUS_ERR_INT_ENA` reader - 1: enabled, if an bus error has been detected, the TWAI controller requests the respective interrupt. 0: disable"]
34pub type BUS_ERR_INT_ENA_R = crate::BitReader;
35#[doc = "Field `BUS_ERR_INT_ENA` writer - 1: enabled, if an bus error has been detected, the TWAI controller requests the respective interrupt. 0: disable"]
36pub type BUS_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `IDLE_INT_ENA` reader - 1: enabled, if state of TWAI become IDLE, the TWAI controller requests the respective interrupt. 0: disable"]
38pub type IDLE_INT_ENA_R = crate::BitReader;
39impl R {
40 #[doc = "Bit 0 - 1: enabled, when the receive buffer status is 'full' the TWAI controller requests the respective interrupt. 0: disable"]
41 #[inline(always)]
42 pub fn ext_receive_int_ena(&self) -> EXT_RECEIVE_INT_ENA_R {
43 EXT_RECEIVE_INT_ENA_R::new((self.bits & 1) != 0)
44 }
45 #[doc = "Bit 1 - 1: enabled, when a message has been successfully transmitted or the transmit buffer is accessible again (e.g. after an abort transmission command), the TWAI controller requests the respective interrupt. 0: disable"]
46 #[inline(always)]
47 pub fn ext_transmit_int_ena(&self) -> EXT_TRANSMIT_INT_ENA_R {
48 EXT_TRANSMIT_INT_ENA_R::new(((self.bits >> 1) & 1) != 0)
49 }
50 #[doc = "Bit 2 - 1: enabled, if the error or bus status change (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable"]
51 #[inline(always)]
52 pub fn ext_err_warning_int_ena(&self) -> EXT_ERR_WARNING_INT_ENA_R {
53 EXT_ERR_WARNING_INT_ENA_R::new(((self.bits >> 2) & 1) != 0)
54 }
55 #[doc = "Bit 3 - 1: enabled, if the data overrun status bit is set (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable"]
56 #[inline(always)]
57 pub fn ext_data_overrun_int_ena(&self) -> EXT_DATA_OVERRUN_INT_ENA_R {
58 EXT_DATA_OVERRUN_INT_ENA_R::new(((self.bits >> 3) & 1) != 0)
59 }
60 #[doc = "Bit 4 - enable the timestamp counter overflow interrupt request."]
61 #[inline(always)]
62 pub fn ts_counter_ovfl_int_ena(&self) -> TS_COUNTER_OVFL_INT_ENA_R {
63 TS_COUNTER_OVFL_INT_ENA_R::new(((self.bits >> 4) & 1) != 0)
64 }
65 #[doc = "Bit 5 - 1: enabled, if the error status of the TWAI controller changes from error active to error passive or vice versa, the respective interrupt is requested. 0: disable"]
66 #[inline(always)]
67 pub fn err_passive_int_ena(&self) -> ERR_PASSIVE_INT_ENA_R {
68 ERR_PASSIVE_INT_ENA_R::new(((self.bits >> 5) & 1) != 0)
69 }
70 #[doc = "Bit 6 - 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt is requested. 0: disable"]
71 #[inline(always)]
72 pub fn arbitration_lost_int_ena(&self) -> ARBITRATION_LOST_INT_ENA_R {
73 ARBITRATION_LOST_INT_ENA_R::new(((self.bits >> 6) & 1) != 0)
74 }
75 #[doc = "Bit 7 - 1: enabled, if an bus error has been detected, the TWAI controller requests the respective interrupt. 0: disable"]
76 #[inline(always)]
77 pub fn bus_err_int_ena(&self) -> BUS_ERR_INT_ENA_R {
78 BUS_ERR_INT_ENA_R::new(((self.bits >> 7) & 1) != 0)
79 }
80 #[doc = "Bit 8 - 1: enabled, if state of TWAI become IDLE, the TWAI controller requests the respective interrupt. 0: disable"]
81 #[inline(always)]
82 pub fn idle_int_ena(&self) -> IDLE_INT_ENA_R {
83 IDLE_INT_ENA_R::new(((self.bits >> 8) & 1) != 0)
84 }
85}
86#[cfg(feature = "impl-register-debug")]
87impl core::fmt::Debug for R {
88 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
89 f.debug_struct("INTERRUPT_ENABLE")
90 .field(
91 "ext_receive_int_ena",
92 &format_args!("{}", self.ext_receive_int_ena().bit()),
93 )
94 .field(
95 "ext_transmit_int_ena",
96 &format_args!("{}", self.ext_transmit_int_ena().bit()),
97 )
98 .field(
99 "ext_err_warning_int_ena",
100 &format_args!("{}", self.ext_err_warning_int_ena().bit()),
101 )
102 .field(
103 "ext_data_overrun_int_ena",
104 &format_args!("{}", self.ext_data_overrun_int_ena().bit()),
105 )
106 .field(
107 "ts_counter_ovfl_int_ena",
108 &format_args!("{}", self.ts_counter_ovfl_int_ena().bit()),
109 )
110 .field(
111 "err_passive_int_ena",
112 &format_args!("{}", self.err_passive_int_ena().bit()),
113 )
114 .field(
115 "arbitration_lost_int_ena",
116 &format_args!("{}", self.arbitration_lost_int_ena().bit()),
117 )
118 .field(
119 "bus_err_int_ena",
120 &format_args!("{}", self.bus_err_int_ena().bit()),
121 )
122 .field(
123 "idle_int_ena",
124 &format_args!("{}", self.idle_int_ena().bit()),
125 )
126 .finish()
127 }
128}
129#[cfg(feature = "impl-register-debug")]
130impl core::fmt::Debug for crate::generic::Reg<INTERRUPT_ENABLE_SPEC> {
131 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
132 core::fmt::Debug::fmt(&self.read(), f)
133 }
134}
135impl W {
136 #[doc = "Bit 0 - 1: enabled, when the receive buffer status is 'full' the TWAI controller requests the respective interrupt. 0: disable"]
137 #[inline(always)]
138 #[must_use]
139 pub fn ext_receive_int_ena(&mut self) -> EXT_RECEIVE_INT_ENA_W<INTERRUPT_ENABLE_SPEC> {
140 EXT_RECEIVE_INT_ENA_W::new(self, 0)
141 }
142 #[doc = "Bit 1 - 1: enabled, when a message has been successfully transmitted or the transmit buffer is accessible again (e.g. after an abort transmission command), the TWAI controller requests the respective interrupt. 0: disable"]
143 #[inline(always)]
144 #[must_use]
145 pub fn ext_transmit_int_ena(&mut self) -> EXT_TRANSMIT_INT_ENA_W<INTERRUPT_ENABLE_SPEC> {
146 EXT_TRANSMIT_INT_ENA_W::new(self, 1)
147 }
148 #[doc = "Bit 2 - 1: enabled, if the error or bus status change (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable"]
149 #[inline(always)]
150 #[must_use]
151 pub fn ext_err_warning_int_ena(&mut self) -> EXT_ERR_WARNING_INT_ENA_W<INTERRUPT_ENABLE_SPEC> {
152 EXT_ERR_WARNING_INT_ENA_W::new(self, 2)
153 }
154 #[doc = "Bit 3 - 1: enabled, if the data overrun status bit is set (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable"]
155 #[inline(always)]
156 #[must_use]
157 pub fn ext_data_overrun_int_ena(
158 &mut self,
159 ) -> EXT_DATA_OVERRUN_INT_ENA_W<INTERRUPT_ENABLE_SPEC> {
160 EXT_DATA_OVERRUN_INT_ENA_W::new(self, 3)
161 }
162 #[doc = "Bit 4 - enable the timestamp counter overflow interrupt request."]
163 #[inline(always)]
164 #[must_use]
165 pub fn ts_counter_ovfl_int_ena(&mut self) -> TS_COUNTER_OVFL_INT_ENA_W<INTERRUPT_ENABLE_SPEC> {
166 TS_COUNTER_OVFL_INT_ENA_W::new(self, 4)
167 }
168 #[doc = "Bit 5 - 1: enabled, if the error status of the TWAI controller changes from error active to error passive or vice versa, the respective interrupt is requested. 0: disable"]
169 #[inline(always)]
170 #[must_use]
171 pub fn err_passive_int_ena(&mut self) -> ERR_PASSIVE_INT_ENA_W<INTERRUPT_ENABLE_SPEC> {
172 ERR_PASSIVE_INT_ENA_W::new(self, 5)
173 }
174 #[doc = "Bit 6 - 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt is requested. 0: disable"]
175 #[inline(always)]
176 #[must_use]
177 pub fn arbitration_lost_int_ena(
178 &mut self,
179 ) -> ARBITRATION_LOST_INT_ENA_W<INTERRUPT_ENABLE_SPEC> {
180 ARBITRATION_LOST_INT_ENA_W::new(self, 6)
181 }
182 #[doc = "Bit 7 - 1: enabled, if an bus error has been detected, the TWAI controller requests the respective interrupt. 0: disable"]
183 #[inline(always)]
184 #[must_use]
185 pub fn bus_err_int_ena(&mut self) -> BUS_ERR_INT_ENA_W<INTERRUPT_ENABLE_SPEC> {
186 BUS_ERR_INT_ENA_W::new(self, 7)
187 }
188}
189#[doc = "Interrupt enable register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`interrupt_enable::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interrupt_enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
190pub struct INTERRUPT_ENABLE_SPEC;
191impl crate::RegisterSpec for INTERRUPT_ENABLE_SPEC {
192 type Ux = u32;
193}
194#[doc = "`read()` method returns [`interrupt_enable::R`](R) reader structure"]
195impl crate::Readable for INTERRUPT_ENABLE_SPEC {}
196#[doc = "`write(|w| ..)` method takes [`interrupt_enable::W`](W) writer structure"]
197impl crate::Writable for INTERRUPT_ENABLE_SPEC {
198 type Safety = crate::Unsafe;
199 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
200 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
201}
202#[doc = "`reset()` method sets INTERRUPT_ENABLE to value 0"]
203impl crate::Resettable for INTERRUPT_ENABLE_SPEC {
204 const RESET_VALUE: u32 = 0;
205}