1#[doc = "Register `INT_RAW` reader"]
2pub type R = crate::R<INT_RAW_SPEC>;
3#[doc = "Register `INT_RAW` writer"]
4pub type W = crate::W<INT_RAW_SPEC>;
5#[doc = "Field `RXFIFO_FULL_INT_RAW` reader - This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies."]
6pub type RXFIFO_FULL_INT_RAW_R = crate::BitReader;
7#[doc = "Field `RXFIFO_FULL_INT_RAW` writer - This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies."]
8pub type RXFIFO_FULL_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `TXFIFO_EMPTY_INT_RAW` reader - This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies ."]
10pub type TXFIFO_EMPTY_INT_RAW_R = crate::BitReader;
11#[doc = "Field `TXFIFO_EMPTY_INT_RAW` writer - This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies ."]
12pub type TXFIFO_EMPTY_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `PARITY_ERR_INT_RAW` reader - This interrupt raw bit turns to high level when receiver detects a parity error in the data."]
14pub type PARITY_ERR_INT_RAW_R = crate::BitReader;
15#[doc = "Field `PARITY_ERR_INT_RAW` writer - This interrupt raw bit turns to high level when receiver detects a parity error in the data."]
16pub type PARITY_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `FRM_ERR_INT_RAW` reader - This interrupt raw bit turns to high level when receiver detects a data frame error ."]
18pub type FRM_ERR_INT_RAW_R = crate::BitReader;
19#[doc = "Field `FRM_ERR_INT_RAW` writer - This interrupt raw bit turns to high level when receiver detects a data frame error ."]
20pub type FRM_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `RXFIFO_OVF_INT_RAW` reader - This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store."]
22pub type RXFIFO_OVF_INT_RAW_R = crate::BitReader;
23#[doc = "Field `RXFIFO_OVF_INT_RAW` writer - This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store."]
24pub type RXFIFO_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `DSR_CHG_INT_RAW` reader - This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal."]
26pub type DSR_CHG_INT_RAW_R = crate::BitReader;
27#[doc = "Field `DSR_CHG_INT_RAW` writer - This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal."]
28pub type DSR_CHG_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `CTS_CHG_INT_RAW` reader - This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal."]
30pub type CTS_CHG_INT_RAW_R = crate::BitReader;
31#[doc = "Field `CTS_CHG_INT_RAW` writer - This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal."]
32pub type CTS_CHG_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `BRK_DET_INT_RAW` reader - This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit."]
34pub type BRK_DET_INT_RAW_R = crate::BitReader;
35#[doc = "Field `BRK_DET_INT_RAW` writer - This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit."]
36pub type BRK_DET_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `RXFIFO_TOUT_INT_RAW` reader - This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte."]
38pub type RXFIFO_TOUT_INT_RAW_R = crate::BitReader;
39#[doc = "Field `RXFIFO_TOUT_INT_RAW` writer - This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte."]
40pub type RXFIFO_TOUT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `SW_XON_INT_RAW` reader - This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1."]
42pub type SW_XON_INT_RAW_R = crate::BitReader;
43#[doc = "Field `SW_XON_INT_RAW` writer - This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1."]
44pub type SW_XON_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `SW_XOFF_INT_RAW` reader - This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1."]
46pub type SW_XOFF_INT_RAW_R = crate::BitReader;
47#[doc = "Field `SW_XOFF_INT_RAW` writer - This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1."]
48pub type SW_XOFF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `GLITCH_DET_INT_RAW` reader - This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit."]
50pub type GLITCH_DET_INT_RAW_R = crate::BitReader;
51#[doc = "Field `GLITCH_DET_INT_RAW` writer - This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit."]
52pub type GLITCH_DET_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `TX_BRK_DONE_INT_RAW` reader - This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent."]
54pub type TX_BRK_DONE_INT_RAW_R = crate::BitReader;
55#[doc = "Field `TX_BRK_DONE_INT_RAW` writer - This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent."]
56pub type TX_BRK_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `TX_BRK_IDLE_DONE_INT_RAW` reader - This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data."]
58pub type TX_BRK_IDLE_DONE_INT_RAW_R = crate::BitReader;
59#[doc = "Field `TX_BRK_IDLE_DONE_INT_RAW` writer - This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data."]
60pub type TX_BRK_IDLE_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `TX_DONE_INT_RAW` reader - This interrupt raw bit turns to high level when transmitter has send out all data in FIFO."]
62pub type TX_DONE_INT_RAW_R = crate::BitReader;
63#[doc = "Field `TX_DONE_INT_RAW` writer - This interrupt raw bit turns to high level when transmitter has send out all data in FIFO."]
64pub type TX_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `AT_CMD_CHAR_DET_INT_RAW` reader - This interrupt raw bit turns to high level when receiver detects the configured at_cmd char."]
66pub type AT_CMD_CHAR_DET_INT_RAW_R = crate::BitReader;
67#[doc = "Field `AT_CMD_CHAR_DET_INT_RAW` writer - This interrupt raw bit turns to high level when receiver detects the configured at_cmd char."]
68pub type AT_CMD_CHAR_DET_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `WAKEUP_INT_RAW` reader - This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode."]
70pub type WAKEUP_INT_RAW_R = crate::BitReader;
71#[doc = "Field `WAKEUP_INT_RAW` writer - This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode."]
72pub type WAKEUP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
73impl R {
74 #[doc = "Bit 0 - This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies."]
75 #[inline(always)]
76 pub fn rxfifo_full_int_raw(&self) -> RXFIFO_FULL_INT_RAW_R {
77 RXFIFO_FULL_INT_RAW_R::new((self.bits & 1) != 0)
78 }
79 #[doc = "Bit 1 - This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies ."]
80 #[inline(always)]
81 pub fn txfifo_empty_int_raw(&self) -> TXFIFO_EMPTY_INT_RAW_R {
82 TXFIFO_EMPTY_INT_RAW_R::new(((self.bits >> 1) & 1) != 0)
83 }
84 #[doc = "Bit 2 - This interrupt raw bit turns to high level when receiver detects a parity error in the data."]
85 #[inline(always)]
86 pub fn parity_err_int_raw(&self) -> PARITY_ERR_INT_RAW_R {
87 PARITY_ERR_INT_RAW_R::new(((self.bits >> 2) & 1) != 0)
88 }
89 #[doc = "Bit 3 - This interrupt raw bit turns to high level when receiver detects a data frame error ."]
90 #[inline(always)]
91 pub fn frm_err_int_raw(&self) -> FRM_ERR_INT_RAW_R {
92 FRM_ERR_INT_RAW_R::new(((self.bits >> 3) & 1) != 0)
93 }
94 #[doc = "Bit 4 - This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store."]
95 #[inline(always)]
96 pub fn rxfifo_ovf_int_raw(&self) -> RXFIFO_OVF_INT_RAW_R {
97 RXFIFO_OVF_INT_RAW_R::new(((self.bits >> 4) & 1) != 0)
98 }
99 #[doc = "Bit 5 - This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal."]
100 #[inline(always)]
101 pub fn dsr_chg_int_raw(&self) -> DSR_CHG_INT_RAW_R {
102 DSR_CHG_INT_RAW_R::new(((self.bits >> 5) & 1) != 0)
103 }
104 #[doc = "Bit 6 - This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal."]
105 #[inline(always)]
106 pub fn cts_chg_int_raw(&self) -> CTS_CHG_INT_RAW_R {
107 CTS_CHG_INT_RAW_R::new(((self.bits >> 6) & 1) != 0)
108 }
109 #[doc = "Bit 7 - This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit."]
110 #[inline(always)]
111 pub fn brk_det_int_raw(&self) -> BRK_DET_INT_RAW_R {
112 BRK_DET_INT_RAW_R::new(((self.bits >> 7) & 1) != 0)
113 }
114 #[doc = "Bit 8 - This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte."]
115 #[inline(always)]
116 pub fn rxfifo_tout_int_raw(&self) -> RXFIFO_TOUT_INT_RAW_R {
117 RXFIFO_TOUT_INT_RAW_R::new(((self.bits >> 8) & 1) != 0)
118 }
119 #[doc = "Bit 9 - This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1."]
120 #[inline(always)]
121 pub fn sw_xon_int_raw(&self) -> SW_XON_INT_RAW_R {
122 SW_XON_INT_RAW_R::new(((self.bits >> 9) & 1) != 0)
123 }
124 #[doc = "Bit 10 - This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1."]
125 #[inline(always)]
126 pub fn sw_xoff_int_raw(&self) -> SW_XOFF_INT_RAW_R {
127 SW_XOFF_INT_RAW_R::new(((self.bits >> 10) & 1) != 0)
128 }
129 #[doc = "Bit 11 - This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit."]
130 #[inline(always)]
131 pub fn glitch_det_int_raw(&self) -> GLITCH_DET_INT_RAW_R {
132 GLITCH_DET_INT_RAW_R::new(((self.bits >> 11) & 1) != 0)
133 }
134 #[doc = "Bit 12 - This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent."]
135 #[inline(always)]
136 pub fn tx_brk_done_int_raw(&self) -> TX_BRK_DONE_INT_RAW_R {
137 TX_BRK_DONE_INT_RAW_R::new(((self.bits >> 12) & 1) != 0)
138 }
139 #[doc = "Bit 13 - This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data."]
140 #[inline(always)]
141 pub fn tx_brk_idle_done_int_raw(&self) -> TX_BRK_IDLE_DONE_INT_RAW_R {
142 TX_BRK_IDLE_DONE_INT_RAW_R::new(((self.bits >> 13) & 1) != 0)
143 }
144 #[doc = "Bit 14 - This interrupt raw bit turns to high level when transmitter has send out all data in FIFO."]
145 #[inline(always)]
146 pub fn tx_done_int_raw(&self) -> TX_DONE_INT_RAW_R {
147 TX_DONE_INT_RAW_R::new(((self.bits >> 14) & 1) != 0)
148 }
149 #[doc = "Bit 18 - This interrupt raw bit turns to high level when receiver detects the configured at_cmd char."]
150 #[inline(always)]
151 pub fn at_cmd_char_det_int_raw(&self) -> AT_CMD_CHAR_DET_INT_RAW_R {
152 AT_CMD_CHAR_DET_INT_RAW_R::new(((self.bits >> 18) & 1) != 0)
153 }
154 #[doc = "Bit 19 - This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode."]
155 #[inline(always)]
156 pub fn wakeup_int_raw(&self) -> WAKEUP_INT_RAW_R {
157 WAKEUP_INT_RAW_R::new(((self.bits >> 19) & 1) != 0)
158 }
159}
160#[cfg(feature = "impl-register-debug")]
161impl core::fmt::Debug for R {
162 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
163 f.debug_struct("INT_RAW")
164 .field(
165 "rxfifo_full_int_raw",
166 &format_args!("{}", self.rxfifo_full_int_raw().bit()),
167 )
168 .field(
169 "txfifo_empty_int_raw",
170 &format_args!("{}", self.txfifo_empty_int_raw().bit()),
171 )
172 .field(
173 "parity_err_int_raw",
174 &format_args!("{}", self.parity_err_int_raw().bit()),
175 )
176 .field(
177 "frm_err_int_raw",
178 &format_args!("{}", self.frm_err_int_raw().bit()),
179 )
180 .field(
181 "rxfifo_ovf_int_raw",
182 &format_args!("{}", self.rxfifo_ovf_int_raw().bit()),
183 )
184 .field(
185 "dsr_chg_int_raw",
186 &format_args!("{}", self.dsr_chg_int_raw().bit()),
187 )
188 .field(
189 "cts_chg_int_raw",
190 &format_args!("{}", self.cts_chg_int_raw().bit()),
191 )
192 .field(
193 "brk_det_int_raw",
194 &format_args!("{}", self.brk_det_int_raw().bit()),
195 )
196 .field(
197 "rxfifo_tout_int_raw",
198 &format_args!("{}", self.rxfifo_tout_int_raw().bit()),
199 )
200 .field(
201 "sw_xon_int_raw",
202 &format_args!("{}", self.sw_xon_int_raw().bit()),
203 )
204 .field(
205 "sw_xoff_int_raw",
206 &format_args!("{}", self.sw_xoff_int_raw().bit()),
207 )
208 .field(
209 "glitch_det_int_raw",
210 &format_args!("{}", self.glitch_det_int_raw().bit()),
211 )
212 .field(
213 "tx_brk_done_int_raw",
214 &format_args!("{}", self.tx_brk_done_int_raw().bit()),
215 )
216 .field(
217 "tx_brk_idle_done_int_raw",
218 &format_args!("{}", self.tx_brk_idle_done_int_raw().bit()),
219 )
220 .field(
221 "tx_done_int_raw",
222 &format_args!("{}", self.tx_done_int_raw().bit()),
223 )
224 .field(
225 "at_cmd_char_det_int_raw",
226 &format_args!("{}", self.at_cmd_char_det_int_raw().bit()),
227 )
228 .field(
229 "wakeup_int_raw",
230 &format_args!("{}", self.wakeup_int_raw().bit()),
231 )
232 .finish()
233 }
234}
235#[cfg(feature = "impl-register-debug")]
236impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
237 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
238 core::fmt::Debug::fmt(&self.read(), f)
239 }
240}
241impl W {
242 #[doc = "Bit 0 - This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies."]
243 #[inline(always)]
244 #[must_use]
245 pub fn rxfifo_full_int_raw(&mut self) -> RXFIFO_FULL_INT_RAW_W<INT_RAW_SPEC> {
246 RXFIFO_FULL_INT_RAW_W::new(self, 0)
247 }
248 #[doc = "Bit 1 - This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies ."]
249 #[inline(always)]
250 #[must_use]
251 pub fn txfifo_empty_int_raw(&mut self) -> TXFIFO_EMPTY_INT_RAW_W<INT_RAW_SPEC> {
252 TXFIFO_EMPTY_INT_RAW_W::new(self, 1)
253 }
254 #[doc = "Bit 2 - This interrupt raw bit turns to high level when receiver detects a parity error in the data."]
255 #[inline(always)]
256 #[must_use]
257 pub fn parity_err_int_raw(&mut self) -> PARITY_ERR_INT_RAW_W<INT_RAW_SPEC> {
258 PARITY_ERR_INT_RAW_W::new(self, 2)
259 }
260 #[doc = "Bit 3 - This interrupt raw bit turns to high level when receiver detects a data frame error ."]
261 #[inline(always)]
262 #[must_use]
263 pub fn frm_err_int_raw(&mut self) -> FRM_ERR_INT_RAW_W<INT_RAW_SPEC> {
264 FRM_ERR_INT_RAW_W::new(self, 3)
265 }
266 #[doc = "Bit 4 - This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store."]
267 #[inline(always)]
268 #[must_use]
269 pub fn rxfifo_ovf_int_raw(&mut self) -> RXFIFO_OVF_INT_RAW_W<INT_RAW_SPEC> {
270 RXFIFO_OVF_INT_RAW_W::new(self, 4)
271 }
272 #[doc = "Bit 5 - This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal."]
273 #[inline(always)]
274 #[must_use]
275 pub fn dsr_chg_int_raw(&mut self) -> DSR_CHG_INT_RAW_W<INT_RAW_SPEC> {
276 DSR_CHG_INT_RAW_W::new(self, 5)
277 }
278 #[doc = "Bit 6 - This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal."]
279 #[inline(always)]
280 #[must_use]
281 pub fn cts_chg_int_raw(&mut self) -> CTS_CHG_INT_RAW_W<INT_RAW_SPEC> {
282 CTS_CHG_INT_RAW_W::new(self, 6)
283 }
284 #[doc = "Bit 7 - This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit."]
285 #[inline(always)]
286 #[must_use]
287 pub fn brk_det_int_raw(&mut self) -> BRK_DET_INT_RAW_W<INT_RAW_SPEC> {
288 BRK_DET_INT_RAW_W::new(self, 7)
289 }
290 #[doc = "Bit 8 - This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte."]
291 #[inline(always)]
292 #[must_use]
293 pub fn rxfifo_tout_int_raw(&mut self) -> RXFIFO_TOUT_INT_RAW_W<INT_RAW_SPEC> {
294 RXFIFO_TOUT_INT_RAW_W::new(self, 8)
295 }
296 #[doc = "Bit 9 - This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1."]
297 #[inline(always)]
298 #[must_use]
299 pub fn sw_xon_int_raw(&mut self) -> SW_XON_INT_RAW_W<INT_RAW_SPEC> {
300 SW_XON_INT_RAW_W::new(self, 9)
301 }
302 #[doc = "Bit 10 - This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1."]
303 #[inline(always)]
304 #[must_use]
305 pub fn sw_xoff_int_raw(&mut self) -> SW_XOFF_INT_RAW_W<INT_RAW_SPEC> {
306 SW_XOFF_INT_RAW_W::new(self, 10)
307 }
308 #[doc = "Bit 11 - This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit."]
309 #[inline(always)]
310 #[must_use]
311 pub fn glitch_det_int_raw(&mut self) -> GLITCH_DET_INT_RAW_W<INT_RAW_SPEC> {
312 GLITCH_DET_INT_RAW_W::new(self, 11)
313 }
314 #[doc = "Bit 12 - This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent."]
315 #[inline(always)]
316 #[must_use]
317 pub fn tx_brk_done_int_raw(&mut self) -> TX_BRK_DONE_INT_RAW_W<INT_RAW_SPEC> {
318 TX_BRK_DONE_INT_RAW_W::new(self, 12)
319 }
320 #[doc = "Bit 13 - This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data."]
321 #[inline(always)]
322 #[must_use]
323 pub fn tx_brk_idle_done_int_raw(&mut self) -> TX_BRK_IDLE_DONE_INT_RAW_W<INT_RAW_SPEC> {
324 TX_BRK_IDLE_DONE_INT_RAW_W::new(self, 13)
325 }
326 #[doc = "Bit 14 - This interrupt raw bit turns to high level when transmitter has send out all data in FIFO."]
327 #[inline(always)]
328 #[must_use]
329 pub fn tx_done_int_raw(&mut self) -> TX_DONE_INT_RAW_W<INT_RAW_SPEC> {
330 TX_DONE_INT_RAW_W::new(self, 14)
331 }
332 #[doc = "Bit 18 - This interrupt raw bit turns to high level when receiver detects the configured at_cmd char."]
333 #[inline(always)]
334 #[must_use]
335 pub fn at_cmd_char_det_int_raw(&mut self) -> AT_CMD_CHAR_DET_INT_RAW_W<INT_RAW_SPEC> {
336 AT_CMD_CHAR_DET_INT_RAW_W::new(self, 18)
337 }
338 #[doc = "Bit 19 - This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode."]
339 #[inline(always)]
340 #[must_use]
341 pub fn wakeup_int_raw(&mut self) -> WAKEUP_INT_RAW_W<INT_RAW_SPEC> {
342 WAKEUP_INT_RAW_W::new(self, 19)
343 }
344}
345#[doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
346pub struct INT_RAW_SPEC;
347impl crate::RegisterSpec for INT_RAW_SPEC {
348 type Ux = u32;
349}
350#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"]
351impl crate::Readable for INT_RAW_SPEC {}
352#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"]
353impl crate::Writable for INT_RAW_SPEC {
354 type Safety = crate::Unsafe;
355 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
356 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
357}
358#[doc = "`reset()` method sets INT_RAW to value 0x02"]
359impl crate::Resettable for INT_RAW_SPEC {
360 const RESET_VALUE: u32 = 0x02;
361}