Module i3c_mst

Module i3c_mst 

Source
Expand description

I3C Controller (Master)

Modules§

buffer_status_level
BUFFER_STATUS_LEVEL reflects the status level of Buffers in the controller.
buffer_thld_ctrl
In-Band Interrupt Status Threshold Value . Every In Band Interrupt received by I3C controller generates an IBI status. This field controls the number of IBI status entries in the IBI buffer that trigger the IBI_STATUS_THLD_STAT interrupt.
bus_free_time
NA
data_buffer_status_level
DATA_BUFFER_STATUS_LEVEL reflects the status level of the Buffers in the controller.
data_buffer_thld_ctrl
NA
device_ctrl
DEVICE_CTRL register controls the transfer properties and disposition of controllers capabilities.
device_table
Pointer for Device Address Table
fpga_debug_probe
NA
ibi_notify_ctrl
NA
ibi_sir_req_payload
NA
ibi_sir_req_reject
NA
int_clr
NA
int_raw
NA
int_st
NA
int_st_ena
The Interrupt status will be updated in INTR_STATUS register if corresponding Status Enable bit set.
present_state0
NA
present_state1
NA
reset_ctrl
NA
rnd_eco_cs
NA
rnd_eco_high
NA
rnd_eco_low
NA
scl_ext_low_time
NA
scl_i2c_fm_time
NA
scl_i2c_fmp_time
NA
scl_i3c_mst_od_time
NA
scl_i3c_mst_pp_time
NA
scl_rstart_setup
NA
scl_start_hold
NA
scl_stop_hold
NA
scl_stop_setup
NA
scl_termn_t_ext_low_time
NA
sda_hold_time
NA
sda_sample_time
NA
time_out_value
NA
ver_id
NA
ver_type
NA

Structs§

RegisterBlock
Register block

Type Aliases§

BUFFER_STATUS_LEVEL
BUFFER_STATUS_LEVEL (r) register accessor: BUFFER_STATUS_LEVEL reflects the status level of Buffers in the controller.
BUFFER_THLD_CTRL
BUFFER_THLD_CTRL (rw) register accessor: In-Band Interrupt Status Threshold Value . Every In Band Interrupt received by I3C controller generates an IBI status. This field controls the number of IBI status entries in the IBI buffer that trigger the IBI_STATUS_THLD_STAT interrupt.
BUS_FREE_TIME
BUS_FREE_TIME (rw) register accessor: NA
DATA_BUFFER_STATUS_LEVEL
DATA_BUFFER_STATUS_LEVEL (r) register accessor: DATA_BUFFER_STATUS_LEVEL reflects the status level of the Buffers in the controller.
DATA_BUFFER_THLD_CTRL
DATA_BUFFER_THLD_CTRL (rw) register accessor: NA
DEVICE_CTRL
DEVICE_CTRL (rw) register accessor: DEVICE_CTRL register controls the transfer properties and disposition of controllers capabilities.
DEVICE_TABLE
DEVICE_TABLE (rw) register accessor: Pointer for Device Address Table
FPGA_DEBUG_PROBE
FPGA_DEBUG_PROBE (rw) register accessor: NA
IBI_NOTIFY_CTRL
IBI_NOTIFY_CTRL (rw) register accessor: NA
IBI_SIR_REQ_PAYLOAD
IBI_SIR_REQ_PAYLOAD (rw) register accessor: NA
IBI_SIR_REQ_REJECT
IBI_SIR_REQ_REJECT (rw) register accessor: NA
INT_CLR
INT_CLR (w) register accessor: NA
INT_RAW
INT_RAW (rw) register accessor: NA
INT_ST
INT_ST (r) register accessor: NA
INT_ST_ENA
INT_ST_ENA (rw) register accessor: The Interrupt status will be updated in INTR_STATUS register if corresponding Status Enable bit set.
PRESENT_STATE0
PRESENT_STATE0 (r) register accessor: NA
PRESENT_STATE1
PRESENT_STATE1 (r) register accessor: NA
RESET_CTRL
RESET_CTRL (rw) register accessor: NA
RND_ECO_CS
RND_ECO_CS (rw) register accessor: NA
RND_ECO_HIGH
RND_ECO_HIGH (rw) register accessor: NA
RND_ECO_LOW
RND_ECO_LOW (rw) register accessor: NA
SCL_EXT_LOW_TIME
SCL_EXT_LOW_TIME (rw) register accessor: NA
SCL_I2C_FMP_TIME
SCL_I2C_FMP_TIME (rw) register accessor: NA
SCL_I2C_FM_TIME
SCL_I2C_FM_TIME (rw) register accessor: NA
SCL_I3C_MST_OD_TIME
SCL_I3C_MST_OD_TIME (rw) register accessor: NA
SCL_I3C_MST_PP_TIME
SCL_I3C_MST_PP_TIME (rw) register accessor: NA
SCL_RSTART_SETUP
SCL_RSTART_SETUP (rw) register accessor: NA
SCL_START_HOLD
SCL_START_HOLD (rw) register accessor: NA
SCL_STOP_HOLD
SCL_STOP_HOLD (rw) register accessor: NA
SCL_STOP_SETUP
SCL_STOP_SETUP (rw) register accessor: NA
SCL_TERMN_T_EXT_LOW_TIME
SCL_TERMN_T_EXT_LOW_TIME (rw) register accessor: NA
SDA_HOLD_TIME
SDA_HOLD_TIME (rw) register accessor: NA
SDA_SAMPLE_TIME
SDA_SAMPLE_TIME (rw) register accessor: NA
TIME_OUT_VALUE
TIME_OUT_VALUE (rw) register accessor: NA
VER_ID
VER_ID (rw) register accessor: NA
VER_TYPE
VER_TYPE (rw) register accessor: NA