esp32p4/isp/
dpc_matrix_ctrl.rs

1#[doc = "Register `DPC_MATRIX_CTRL` reader"]
2pub type R = crate::R<DPC_MATRIX_CTRL_SPEC>;
3#[doc = "Register `DPC_MATRIX_CTRL` writer"]
4pub type W = crate::W<DPC_MATRIX_CTRL_SPEC>;
5#[doc = "Field `DPC_TAIL_PIXEN_PULSE_TL` reader - matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and reg_dpc_tail_pixen_pulse_th &lt; reg_dpc_tail_pixen_pulse_tl will enable tail pulse function"]
6pub type DPC_TAIL_PIXEN_PULSE_TL_R = crate::FieldReader;
7#[doc = "Field `DPC_TAIL_PIXEN_PULSE_TL` writer - matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and reg_dpc_tail_pixen_pulse_th &lt; reg_dpc_tail_pixen_pulse_tl will enable tail pulse function"]
8pub type DPC_TAIL_PIXEN_PULSE_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `DPC_TAIL_PIXEN_PULSE_TH` reader - matrix tail pixen high level threshold, must &lt; hnum-1, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and reg_dpc_tail_pixen_pulse_th &lt; reg_dpc_tail_pixen_pulse_tl will enable tail pulse function"]
10pub type DPC_TAIL_PIXEN_PULSE_TH_R = crate::FieldReader;
11#[doc = "Field `DPC_TAIL_PIXEN_PULSE_TH` writer - matrix tail pixen high level threshold, must &lt; hnum-1, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and reg_dpc_tail_pixen_pulse_th &lt; reg_dpc_tail_pixen_pulse_tl will enable tail pulse function"]
12pub type DPC_TAIL_PIXEN_PULSE_TH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
13#[doc = "Field `DPC_PADDING_DATA` reader - this field configures dpc matrix padding data"]
14pub type DPC_PADDING_DATA_R = crate::FieldReader;
15#[doc = "Field `DPC_PADDING_DATA` writer - this field configures dpc matrix padding data"]
16pub type DPC_PADDING_DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
17#[doc = "Field `DPC_PADDING_MODE` reader - this bit configures the padding mode of dpc matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding"]
18pub type DPC_PADDING_MODE_R = crate::BitReader;
19#[doc = "Field `DPC_PADDING_MODE` writer - this bit configures the padding mode of dpc matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding"]
20pub type DPC_PADDING_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bits 0:7 - matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and reg_dpc_tail_pixen_pulse_th &lt; reg_dpc_tail_pixen_pulse_tl will enable tail pulse function"]
23    #[inline(always)]
24    pub fn dpc_tail_pixen_pulse_tl(&self) -> DPC_TAIL_PIXEN_PULSE_TL_R {
25        DPC_TAIL_PIXEN_PULSE_TL_R::new((self.bits & 0xff) as u8)
26    }
27    #[doc = "Bits 8:15 - matrix tail pixen high level threshold, must &lt; hnum-1, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and reg_dpc_tail_pixen_pulse_th &lt; reg_dpc_tail_pixen_pulse_tl will enable tail pulse function"]
28    #[inline(always)]
29    pub fn dpc_tail_pixen_pulse_th(&self) -> DPC_TAIL_PIXEN_PULSE_TH_R {
30        DPC_TAIL_PIXEN_PULSE_TH_R::new(((self.bits >> 8) & 0xff) as u8)
31    }
32    #[doc = "Bits 16:23 - this field configures dpc matrix padding data"]
33    #[inline(always)]
34    pub fn dpc_padding_data(&self) -> DPC_PADDING_DATA_R {
35        DPC_PADDING_DATA_R::new(((self.bits >> 16) & 0xff) as u8)
36    }
37    #[doc = "Bit 24 - this bit configures the padding mode of dpc matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding"]
38    #[inline(always)]
39    pub fn dpc_padding_mode(&self) -> DPC_PADDING_MODE_R {
40        DPC_PADDING_MODE_R::new(((self.bits >> 24) & 1) != 0)
41    }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("DPC_MATRIX_CTRL")
47            .field(
48                "dpc_tail_pixen_pulse_tl",
49                &format_args!("{}", self.dpc_tail_pixen_pulse_tl().bits()),
50            )
51            .field(
52                "dpc_tail_pixen_pulse_th",
53                &format_args!("{}", self.dpc_tail_pixen_pulse_th().bits()),
54            )
55            .field(
56                "dpc_padding_data",
57                &format_args!("{}", self.dpc_padding_data().bits()),
58            )
59            .field(
60                "dpc_padding_mode",
61                &format_args!("{}", self.dpc_padding_mode().bit()),
62            )
63            .finish()
64    }
65}
66#[cfg(feature = "impl-register-debug")]
67impl core::fmt::Debug for crate::generic::Reg<DPC_MATRIX_CTRL_SPEC> {
68    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
69        core::fmt::Debug::fmt(&self.read(), f)
70    }
71}
72impl W {
73    #[doc = "Bits 0:7 - matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and reg_dpc_tail_pixen_pulse_th &lt; reg_dpc_tail_pixen_pulse_tl will enable tail pulse function"]
74    #[inline(always)]
75    #[must_use]
76    pub fn dpc_tail_pixen_pulse_tl(&mut self) -> DPC_TAIL_PIXEN_PULSE_TL_W<DPC_MATRIX_CTRL_SPEC> {
77        DPC_TAIL_PIXEN_PULSE_TL_W::new(self, 0)
78    }
79    #[doc = "Bits 8:15 - matrix tail pixen high level threshold, must &lt; hnum-1, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and reg_dpc_tail_pixen_pulse_th &lt; reg_dpc_tail_pixen_pulse_tl will enable tail pulse function"]
80    #[inline(always)]
81    #[must_use]
82    pub fn dpc_tail_pixen_pulse_th(&mut self) -> DPC_TAIL_PIXEN_PULSE_TH_W<DPC_MATRIX_CTRL_SPEC> {
83        DPC_TAIL_PIXEN_PULSE_TH_W::new(self, 8)
84    }
85    #[doc = "Bits 16:23 - this field configures dpc matrix padding data"]
86    #[inline(always)]
87    #[must_use]
88    pub fn dpc_padding_data(&mut self) -> DPC_PADDING_DATA_W<DPC_MATRIX_CTRL_SPEC> {
89        DPC_PADDING_DATA_W::new(self, 16)
90    }
91    #[doc = "Bit 24 - this bit configures the padding mode of dpc matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding"]
92    #[inline(always)]
93    #[must_use]
94    pub fn dpc_padding_mode(&mut self) -> DPC_PADDING_MODE_W<DPC_MATRIX_CTRL_SPEC> {
95        DPC_PADDING_MODE_W::new(self, 24)
96    }
97}
98#[doc = "dpc pix2matrix ctrl\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpc_matrix_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpc_matrix_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
99pub struct DPC_MATRIX_CTRL_SPEC;
100impl crate::RegisterSpec for DPC_MATRIX_CTRL_SPEC {
101    type Ux = u32;
102}
103#[doc = "`read()` method returns [`dpc_matrix_ctrl::R`](R) reader structure"]
104impl crate::Readable for DPC_MATRIX_CTRL_SPEC {}
105#[doc = "`write(|w| ..)` method takes [`dpc_matrix_ctrl::W`](W) writer structure"]
106impl crate::Writable for DPC_MATRIX_CTRL_SPEC {
107    type Safety = crate::Unsafe;
108    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
109    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
110}
111#[doc = "`reset()` method sets DPC_MATRIX_CTRL to value 0"]
112impl crate::Resettable for DPC_MATRIX_CTRL_SPEC {
113    const RESET_VALUE: u32 = 0;
114}
esp32p4/isp/dpc_matrix_ctrl.rs

esp32p4/isp/
dpc_matrix_ctrl.rs
