1#[doc = "Register `SYNC_L1_CACHE_PRELOAD_INT_RAW` reader"]
2pub type R = crate::R<SYNC_L1_CACHE_PRELOAD_INT_RAW_SPEC>;
3#[doc = "Register `SYNC_L1_CACHE_PRELOAD_INT_RAW` writer"]
4pub type W = crate::W<SYNC_L1_CACHE_PRELOAD_INT_RAW_SPEC>;
5#[doc = "Field `L1_ICACHE0_PLD_DONE_INT_RAW` reader - The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is done."]
6pub type L1_ICACHE0_PLD_DONE_INT_RAW_R = crate::BitReader;
7#[doc = "Field `L1_ICACHE0_PLD_DONE_INT_RAW` writer - The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is done."]
8pub type L1_ICACHE0_PLD_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `L1_ICACHE1_PLD_DONE_INT_RAW` reader - The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is done."]
10pub type L1_ICACHE1_PLD_DONE_INT_RAW_R = crate::BitReader;
11#[doc = "Field `L1_ICACHE1_PLD_DONE_INT_RAW` writer - The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is done."]
12pub type L1_ICACHE1_PLD_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `L1_ICACHE2_PLD_DONE_INT_RAW` reader - Reserved"]
14pub type L1_ICACHE2_PLD_DONE_INT_RAW_R = crate::BitReader;
15#[doc = "Field `L1_ICACHE2_PLD_DONE_INT_RAW` writer - Reserved"]
16pub type L1_ICACHE2_PLD_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `L1_ICACHE3_PLD_DONE_INT_RAW` reader - Reserved"]
18pub type L1_ICACHE3_PLD_DONE_INT_RAW_R = crate::BitReader;
19#[doc = "Field `L1_ICACHE3_PLD_DONE_INT_RAW` writer - Reserved"]
20pub type L1_ICACHE3_PLD_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `L1_DCACHE_PLD_DONE_INT_RAW` reader - The raw bit of the interrupt that occurs only when L1-DCache preload-operation is done."]
22pub type L1_DCACHE_PLD_DONE_INT_RAW_R = crate::BitReader;
23#[doc = "Field `L1_DCACHE_PLD_DONE_INT_RAW` writer - The raw bit of the interrupt that occurs only when L1-DCache preload-operation is done."]
24pub type L1_DCACHE_PLD_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `SYNC_DONE_INT_RAW` reader - The raw bit of the interrupt that occurs only when Cache sync-operation is done."]
26pub type SYNC_DONE_INT_RAW_R = crate::BitReader;
27#[doc = "Field `SYNC_DONE_INT_RAW` writer - The raw bit of the interrupt that occurs only when Cache sync-operation is done."]
28pub type SYNC_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `L1_ICACHE0_PLD_ERR_INT_RAW` reader - The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation error occurs."]
30pub type L1_ICACHE0_PLD_ERR_INT_RAW_R = crate::BitReader;
31#[doc = "Field `L1_ICACHE0_PLD_ERR_INT_RAW` writer - The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation error occurs."]
32pub type L1_ICACHE0_PLD_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `L1_ICACHE1_PLD_ERR_INT_RAW` reader - The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation error occurs."]
34pub type L1_ICACHE1_PLD_ERR_INT_RAW_R = crate::BitReader;
35#[doc = "Field `L1_ICACHE1_PLD_ERR_INT_RAW` writer - The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation error occurs."]
36pub type L1_ICACHE1_PLD_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `L1_ICACHE2_PLD_ERR_INT_RAW` reader - Reserved"]
38pub type L1_ICACHE2_PLD_ERR_INT_RAW_R = crate::BitReader;
39#[doc = "Field `L1_ICACHE2_PLD_ERR_INT_RAW` writer - Reserved"]
40pub type L1_ICACHE2_PLD_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `L1_ICACHE3_PLD_ERR_INT_RAW` reader - Reserved"]
42pub type L1_ICACHE3_PLD_ERR_INT_RAW_R = crate::BitReader;
43#[doc = "Field `L1_ICACHE3_PLD_ERR_INT_RAW` writer - Reserved"]
44pub type L1_ICACHE3_PLD_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `L1_DCACHE_PLD_ERR_INT_RAW` reader - The raw bit of the interrupt that occurs only when L1-DCache preload-operation error occurs."]
46pub type L1_DCACHE_PLD_ERR_INT_RAW_R = crate::BitReader;
47#[doc = "Field `L1_DCACHE_PLD_ERR_INT_RAW` writer - The raw bit of the interrupt that occurs only when L1-DCache preload-operation error occurs."]
48pub type L1_DCACHE_PLD_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `SYNC_ERR_INT_RAW` reader - The raw bit of the interrupt that occurs only when Cache sync-operation error occurs."]
50pub type SYNC_ERR_INT_RAW_R = crate::BitReader;
51#[doc = "Field `SYNC_ERR_INT_RAW` writer - The raw bit of the interrupt that occurs only when Cache sync-operation error occurs."]
52pub type SYNC_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
53impl R {
54 #[doc = "Bit 0 - The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is done."]
55 #[inline(always)]
56 pub fn l1_icache0_pld_done_int_raw(&self) -> L1_ICACHE0_PLD_DONE_INT_RAW_R {
57 L1_ICACHE0_PLD_DONE_INT_RAW_R::new((self.bits & 1) != 0)
58 }
59 #[doc = "Bit 1 - The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is done."]
60 #[inline(always)]
61 pub fn l1_icache1_pld_done_int_raw(&self) -> L1_ICACHE1_PLD_DONE_INT_RAW_R {
62 L1_ICACHE1_PLD_DONE_INT_RAW_R::new(((self.bits >> 1) & 1) != 0)
63 }
64 #[doc = "Bit 2 - Reserved"]
65 #[inline(always)]
66 pub fn l1_icache2_pld_done_int_raw(&self) -> L1_ICACHE2_PLD_DONE_INT_RAW_R {
67 L1_ICACHE2_PLD_DONE_INT_RAW_R::new(((self.bits >> 2) & 1) != 0)
68 }
69 #[doc = "Bit 3 - Reserved"]
70 #[inline(always)]
71 pub fn l1_icache3_pld_done_int_raw(&self) -> L1_ICACHE3_PLD_DONE_INT_RAW_R {
72 L1_ICACHE3_PLD_DONE_INT_RAW_R::new(((self.bits >> 3) & 1) != 0)
73 }
74 #[doc = "Bit 4 - The raw bit of the interrupt that occurs only when L1-DCache preload-operation is done."]
75 #[inline(always)]
76 pub fn l1_dcache_pld_done_int_raw(&self) -> L1_DCACHE_PLD_DONE_INT_RAW_R {
77 L1_DCACHE_PLD_DONE_INT_RAW_R::new(((self.bits >> 4) & 1) != 0)
78 }
79 #[doc = "Bit 6 - The raw bit of the interrupt that occurs only when Cache sync-operation is done."]
80 #[inline(always)]
81 pub fn sync_done_int_raw(&self) -> SYNC_DONE_INT_RAW_R {
82 SYNC_DONE_INT_RAW_R::new(((self.bits >> 6) & 1) != 0)
83 }
84 #[doc = "Bit 7 - The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation error occurs."]
85 #[inline(always)]
86 pub fn l1_icache0_pld_err_int_raw(&self) -> L1_ICACHE0_PLD_ERR_INT_RAW_R {
87 L1_ICACHE0_PLD_ERR_INT_RAW_R::new(((self.bits >> 7) & 1) != 0)
88 }
89 #[doc = "Bit 8 - The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation error occurs."]
90 #[inline(always)]
91 pub fn l1_icache1_pld_err_int_raw(&self) -> L1_ICACHE1_PLD_ERR_INT_RAW_R {
92 L1_ICACHE1_PLD_ERR_INT_RAW_R::new(((self.bits >> 8) & 1) != 0)
93 }
94 #[doc = "Bit 9 - Reserved"]
95 #[inline(always)]
96 pub fn l1_icache2_pld_err_int_raw(&self) -> L1_ICACHE2_PLD_ERR_INT_RAW_R {
97 L1_ICACHE2_PLD_ERR_INT_RAW_R::new(((self.bits >> 9) & 1) != 0)
98 }
99 #[doc = "Bit 10 - Reserved"]
100 #[inline(always)]
101 pub fn l1_icache3_pld_err_int_raw(&self) -> L1_ICACHE3_PLD_ERR_INT_RAW_R {
102 L1_ICACHE3_PLD_ERR_INT_RAW_R::new(((self.bits >> 10) & 1) != 0)
103 }
104 #[doc = "Bit 11 - The raw bit of the interrupt that occurs only when L1-DCache preload-operation error occurs."]
105 #[inline(always)]
106 pub fn l1_dcache_pld_err_int_raw(&self) -> L1_DCACHE_PLD_ERR_INT_RAW_R {
107 L1_DCACHE_PLD_ERR_INT_RAW_R::new(((self.bits >> 11) & 1) != 0)
108 }
109 #[doc = "Bit 13 - The raw bit of the interrupt that occurs only when Cache sync-operation error occurs."]
110 #[inline(always)]
111 pub fn sync_err_int_raw(&self) -> SYNC_ERR_INT_RAW_R {
112 SYNC_ERR_INT_RAW_R::new(((self.bits >> 13) & 1) != 0)
113 }
114}
115#[cfg(feature = "impl-register-debug")]
116impl core::fmt::Debug for R {
117 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
118 f.debug_struct("SYNC_L1_CACHE_PRELOAD_INT_RAW")
119 .field(
120 "l1_icache0_pld_done_int_raw",
121 &format_args!("{}", self.l1_icache0_pld_done_int_raw().bit()),
122 )
123 .field(
124 "l1_icache1_pld_done_int_raw",
125 &format_args!("{}", self.l1_icache1_pld_done_int_raw().bit()),
126 )
127 .field(
128 "l1_icache2_pld_done_int_raw",
129 &format_args!("{}", self.l1_icache2_pld_done_int_raw().bit()),
130 )
131 .field(
132 "l1_icache3_pld_done_int_raw",
133 &format_args!("{}", self.l1_icache3_pld_done_int_raw().bit()),
134 )
135 .field(
136 "l1_dcache_pld_done_int_raw",
137 &format_args!("{}", self.l1_dcache_pld_done_int_raw().bit()),
138 )
139 .field(
140 "sync_done_int_raw",
141 &format_args!("{}", self.sync_done_int_raw().bit()),
142 )
143 .field(
144 "l1_icache0_pld_err_int_raw",
145 &format_args!("{}", self.l1_icache0_pld_err_int_raw().bit()),
146 )
147 .field(
148 "l1_icache1_pld_err_int_raw",
149 &format_args!("{}", self.l1_icache1_pld_err_int_raw().bit()),
150 )
151 .field(
152 "l1_icache2_pld_err_int_raw",
153 &format_args!("{}", self.l1_icache2_pld_err_int_raw().bit()),
154 )
155 .field(
156 "l1_icache3_pld_err_int_raw",
157 &format_args!("{}", self.l1_icache3_pld_err_int_raw().bit()),
158 )
159 .field(
160 "l1_dcache_pld_err_int_raw",
161 &format_args!("{}", self.l1_dcache_pld_err_int_raw().bit()),
162 )
163 .field(
164 "sync_err_int_raw",
165 &format_args!("{}", self.sync_err_int_raw().bit()),
166 )
167 .finish()
168 }
169}
170#[cfg(feature = "impl-register-debug")]
171impl core::fmt::Debug for crate::generic::Reg<SYNC_L1_CACHE_PRELOAD_INT_RAW_SPEC> {
172 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
173 core::fmt::Debug::fmt(&self.read(), f)
174 }
175}
176impl W {
177 #[doc = "Bit 0 - The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is done."]
178 #[inline(always)]
179 #[must_use]
180 pub fn l1_icache0_pld_done_int_raw(
181 &mut self,
182 ) -> L1_ICACHE0_PLD_DONE_INT_RAW_W<SYNC_L1_CACHE_PRELOAD_INT_RAW_SPEC> {
183 L1_ICACHE0_PLD_DONE_INT_RAW_W::new(self, 0)
184 }
185 #[doc = "Bit 1 - The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is done."]
186 #[inline(always)]
187 #[must_use]
188 pub fn l1_icache1_pld_done_int_raw(
189 &mut self,
190 ) -> L1_ICACHE1_PLD_DONE_INT_RAW_W<SYNC_L1_CACHE_PRELOAD_INT_RAW_SPEC> {
191 L1_ICACHE1_PLD_DONE_INT_RAW_W::new(self, 1)
192 }
193 #[doc = "Bit 2 - Reserved"]
194 #[inline(always)]
195 #[must_use]
196 pub fn l1_icache2_pld_done_int_raw(
197 &mut self,
198 ) -> L1_ICACHE2_PLD_DONE_INT_RAW_W<SYNC_L1_CACHE_PRELOAD_INT_RAW_SPEC> {
199 L1_ICACHE2_PLD_DONE_INT_RAW_W::new(self, 2)
200 }
201 #[doc = "Bit 3 - Reserved"]
202 #[inline(always)]
203 #[must_use]
204 pub fn l1_icache3_pld_done_int_raw(
205 &mut self,
206 ) -> L1_ICACHE3_PLD_DONE_INT_RAW_W<SYNC_L1_CACHE_PRELOAD_INT_RAW_SPEC> {
207 L1_ICACHE3_PLD_DONE_INT_RAW_W::new(self, 3)
208 }
209 #[doc = "Bit 4 - The raw bit of the interrupt that occurs only when L1-DCache preload-operation is done."]
210 #[inline(always)]
211 #[must_use]
212 pub fn l1_dcache_pld_done_int_raw(
213 &mut self,
214 ) -> L1_DCACHE_PLD_DONE_INT_RAW_W<SYNC_L1_CACHE_PRELOAD_INT_RAW_SPEC> {
215 L1_DCACHE_PLD_DONE_INT_RAW_W::new(self, 4)
216 }
217 #[doc = "Bit 6 - The raw bit of the interrupt that occurs only when Cache sync-operation is done."]
218 #[inline(always)]
219 #[must_use]
220 pub fn sync_done_int_raw(&mut self) -> SYNC_DONE_INT_RAW_W<SYNC_L1_CACHE_PRELOAD_INT_RAW_SPEC> {
221 SYNC_DONE_INT_RAW_W::new(self, 6)
222 }
223 #[doc = "Bit 7 - The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation error occurs."]
224 #[inline(always)]
225 #[must_use]
226 pub fn l1_icache0_pld_err_int_raw(
227 &mut self,
228 ) -> L1_ICACHE0_PLD_ERR_INT_RAW_W<SYNC_L1_CACHE_PRELOAD_INT_RAW_SPEC> {
229 L1_ICACHE0_PLD_ERR_INT_RAW_W::new(self, 7)
230 }
231 #[doc = "Bit 8 - The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation error occurs."]
232 #[inline(always)]
233 #[must_use]
234 pub fn l1_icache1_pld_err_int_raw(
235 &mut self,
236 ) -> L1_ICACHE1_PLD_ERR_INT_RAW_W<SYNC_L1_CACHE_PRELOAD_INT_RAW_SPEC> {
237 L1_ICACHE1_PLD_ERR_INT_RAW_W::new(self, 8)
238 }
239 #[doc = "Bit 9 - Reserved"]
240 #[inline(always)]
241 #[must_use]
242 pub fn l1_icache2_pld_err_int_raw(
243 &mut self,
244 ) -> L1_ICACHE2_PLD_ERR_INT_RAW_W<SYNC_L1_CACHE_PRELOAD_INT_RAW_SPEC> {
245 L1_ICACHE2_PLD_ERR_INT_RAW_W::new(self, 9)
246 }
247 #[doc = "Bit 10 - Reserved"]
248 #[inline(always)]
249 #[must_use]
250 pub fn l1_icache3_pld_err_int_raw(
251 &mut self,
252 ) -> L1_ICACHE3_PLD_ERR_INT_RAW_W<SYNC_L1_CACHE_PRELOAD_INT_RAW_SPEC> {
253 L1_ICACHE3_PLD_ERR_INT_RAW_W::new(self, 10)
254 }
255 #[doc = "Bit 11 - The raw bit of the interrupt that occurs only when L1-DCache preload-operation error occurs."]
256 #[inline(always)]
257 #[must_use]
258 pub fn l1_dcache_pld_err_int_raw(
259 &mut self,
260 ) -> L1_DCACHE_PLD_ERR_INT_RAW_W<SYNC_L1_CACHE_PRELOAD_INT_RAW_SPEC> {
261 L1_DCACHE_PLD_ERR_INT_RAW_W::new(self, 11)
262 }
263 #[doc = "Bit 13 - The raw bit of the interrupt that occurs only when Cache sync-operation error occurs."]
264 #[inline(always)]
265 #[must_use]
266 pub fn sync_err_int_raw(&mut self) -> SYNC_ERR_INT_RAW_W<SYNC_L1_CACHE_PRELOAD_INT_RAW_SPEC> {
267 SYNC_ERR_INT_RAW_W::new(self, 13)
268 }
269}
270#[doc = "Sync Preload operation Interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_l1_cache_preload_int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sync_l1_cache_preload_int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
271pub struct SYNC_L1_CACHE_PRELOAD_INT_RAW_SPEC;
272impl crate::RegisterSpec for SYNC_L1_CACHE_PRELOAD_INT_RAW_SPEC {
273 type Ux = u32;
274}
275#[doc = "`read()` method returns [`sync_l1_cache_preload_int_raw::R`](R) reader structure"]
276impl crate::Readable for SYNC_L1_CACHE_PRELOAD_INT_RAW_SPEC {}
277#[doc = "`write(|w| ..)` method takes [`sync_l1_cache_preload_int_raw::W`](W) writer structure"]
278impl crate::Writable for SYNC_L1_CACHE_PRELOAD_INT_RAW_SPEC {
279 type Safety = crate::Unsafe;
280 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
281 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
282}
283#[doc = "`reset()` method sets SYNC_L1_CACHE_PRELOAD_INT_RAW to value 0"]
284impl crate::Resettable for SYNC_L1_CACHE_PRELOAD_INT_RAW_SPEC {
285 const RESET_VALUE: u32 = 0;
286}