Module esp32p4::h264_dma

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Expand description

H264 Encoder (DMA)

Modules§

Structs§

Type Aliases§

  • COUNTER_RST
    COUNTER_RST (rw) register accessor: counter reset register
  • DATE
    DATE (rw) register accessor: reserved
  • EXTER_AXI_ERR
    EXTER_AXI_ERR (r) register accessor: exter memory axi err register
  • EXTER_MEM_END_ADDR0
    EXTER_MEM_END_ADDR0 (rw) register accessor: end address of exter memory range0 register
  • EXTER_MEM_END_ADDR1
    EXTER_MEM_END_ADDR1 (rw) register accessor: end address of exter memory range1 register
  • EXTER_MEM_START_ADDR0
    EXTER_MEM_START_ADDR0 (rw) register accessor: Start address of exter memory range0 register
  • EXTER_MEM_START_ADDR1
    EXTER_MEM_START_ADDR1 (rw) register accessor: Start address of exter memory range1 register
  • INFIFO_STATUS_CH0
    INFIFO_STATUS_CH0 (r) register accessor: RX CH0 INFIFO status register
  • INFIFO_STATUS_CH1
    INFIFO_STATUS_CH1 (r) register accessor: RX CH1 INFIFO status register
  • INFIFO_STATUS_CH2
    INFIFO_STATUS_CH2 (r) register accessor: RX CH2 INFIFO status register
  • INFIFO_STATUS_CH3
    INFIFO_STATUS_CH3 (r) register accessor: RX CH3 INFIFO status register
  • INFIFO_STATUS_CH4
    INFIFO_STATUS_CH4 (r) register accessor: RX CH4 INFIFO status register
  • INFIFO_STATUS_CH5
    INFIFO_STATUS_CH5 (r) register accessor: RX CH5 INFIFO status register
  • INTER_AXI_ERR
    INTER_AXI_ERR (r) register accessor: inter memory axi err register
  • INTER_MEM_END_ADDR0
    INTER_MEM_END_ADDR0 (rw) register accessor: end address of inter memory range0 register
  • INTER_MEM_END_ADDR1
    INTER_MEM_END_ADDR1 (rw) register accessor: end address of inter memory range1 register
  • INTER_MEM_START_ADDR0
    INTER_MEM_START_ADDR0 (rw) register accessor: Start address of inter memory range0 register
  • INTER_MEM_START_ADDR1
    INTER_MEM_START_ADDR1 (rw) register accessor: Start address of inter memory range1 register
  • IN_ARB_CH0
    IN_ARB_CH0 (rw) register accessor: RX CH0 arb register
  • IN_ARB_CH1
    IN_ARB_CH1 (rw) register accessor: RX CH1 arb register
  • IN_ARB_CH2
    IN_ARB_CH2 (rw) register accessor: RX CH2 arb register
  • IN_ARB_CH3
    IN_ARB_CH3 (rw) register accessor: RX CH3 arb register
  • IN_ARB_CH4
    IN_ARB_CH4 (rw) register accessor: RX CH4 arb register
  • IN_ARB_CH5
    IN_ARB_CH5 (rw) register accessor: RX CH5 arb register
  • IN_ARB_CONFIG
    IN_ARB_CONFIG (rw) register accessor: reserved
  • IN_BUF_HB_RCV_CH0
    IN_BUF_HB_RCV_CH0 (r) register accessor: rx CH0 buf len hb rcv register
  • IN_BUF_HB_RCV_CH1
    IN_BUF_HB_RCV_CH1 (r) register accessor: rx CH1 buf len hb rcv register
  • IN_BUF_HB_RCV_CH2
    IN_BUF_HB_RCV_CH2 (r) register accessor: rx CH2 buf len hb rcv register
  • IN_BUF_HB_RCV_CH3
    IN_BUF_HB_RCV_CH3 (r) register accessor: rx CH3 buf len hb rcv register
  • IN_BUF_HB_RCV_CH4
    IN_BUF_HB_RCV_CH4 (r) register accessor: rx CH4 buf len hb rcv register
  • IN_BUF_HB_RCV_CH5
    IN_BUF_HB_RCV_CH5 (r) register accessor: rx CH5 buf len hb rcv register
  • IN_CONF0_CH0
    IN_CONF0_CH0 (rw) register accessor: RX CH0 config0 register
  • IN_CONF0_CH1
    IN_CONF0_CH1 (rw) register accessor: RX CH1 config0 register
  • IN_CONF0_CH2
    IN_CONF0_CH2 (rw) register accessor: RX CH2 config0 register
  • IN_CONF0_CH3
    IN_CONF0_CH3 (rw) register accessor: RX CH3 config0 register
  • IN_CONF0_CH4
    IN_CONF0_CH4 (rw) register accessor: RX CH4 config0 register
  • IN_CONF0_CH5
    IN_CONF0_CH5 (rw) register accessor: RX CH5 config0 register
  • IN_CONF1_CH5
    IN_CONF1_CH5 (rw) register accessor: RX CH5 config1 register
  • IN_CONF2_CH5
    IN_CONF2_CH5 (rw) register accessor: RX CH5 config2 register
  • IN_CONF3_CH5
    IN_CONF3_CH5 (rw) register accessor: RX CH5 config3 register
  • IN_DSCR_BF0_CH0
    IN_DSCR_BF0_CH0 (r) register accessor: RX CH0 last dscr addr register
  • IN_DSCR_BF0_CH1
    IN_DSCR_BF0_CH1 (r) register accessor: RX CH1 last dscr addr register
  • IN_DSCR_BF0_CH2
    IN_DSCR_BF0_CH2 (r) register accessor: RX CH2 last dscr addr register
  • IN_DSCR_BF0_CH3
    IN_DSCR_BF0_CH3 (r) register accessor: RX CH3 last dscr addr register
  • IN_DSCR_BF0_CH4
    IN_DSCR_BF0_CH4 (r) register accessor: RX CH4 last dscr addr register
  • IN_DSCR_BF1_CH0
    IN_DSCR_BF1_CH0 (r) register accessor: RX CH0 second-to-last dscr addr register
  • IN_DSCR_BF1_CH1
    IN_DSCR_BF1_CH1 (r) register accessor: RX CH1 second-to-last dscr addr register
  • IN_DSCR_BF1_CH2
    IN_DSCR_BF1_CH2 (r) register accessor: RX CH2 second-to-last dscr addr register
  • IN_DSCR_BF1_CH3
    IN_DSCR_BF1_CH3 (r) register accessor: RX CH3 second-to-last dscr addr register
  • IN_DSCR_BF1_CH4
    IN_DSCR_BF1_CH4 (r) register accessor: RX CH4 second-to-last dscr addr register
  • IN_DSCR_CH0
    IN_DSCR_CH0 (r) register accessor: RX CH0 next dscr addr register
  • IN_DSCR_CH1
    IN_DSCR_CH1 (r) register accessor: RX CH1 next dscr addr register
  • IN_DSCR_CH2
    IN_DSCR_CH2 (r) register accessor: RX CH2 next dscr addr register
  • IN_DSCR_CH3
    IN_DSCR_CH3 (r) register accessor: RX CH3 next dscr addr register
  • IN_DSCR_CH4
    IN_DSCR_CH4 (r) register accessor: RX CH4 next dscr addr register
  • IN_ERR_EOF_DES_ADDR_CH0
    IN_ERR_EOF_DES_ADDR_CH0 (r) register accessor: RX CH0 err eof des addr register
  • IN_ERR_EOF_DES_ADDR_CH1
    IN_ERR_EOF_DES_ADDR_CH1 (r) register accessor: RX CH1 err eof des addr register
  • IN_ERR_EOF_DES_ADDR_CH2
    IN_ERR_EOF_DES_ADDR_CH2 (r) register accessor: RX CH2 err eof des addr register
  • IN_ERR_EOF_DES_ADDR_CH3
    IN_ERR_EOF_DES_ADDR_CH3 (r) register accessor: RX CH3 err eof des addr register
  • IN_ERR_EOF_DES_ADDR_CH4
    IN_ERR_EOF_DES_ADDR_CH4 (r) register accessor: RX CH4 err eof des addr register
  • IN_ETM_CONF_CH0
    IN_ETM_CONF_CH0 (rw) register accessor: RX CH0 ETM config register
  • IN_ETM_CONF_CH1
    IN_ETM_CONF_CH1 (rw) register accessor: RX CH1 ETM config register
  • IN_ETM_CONF_CH2
    IN_ETM_CONF_CH2 (rw) register accessor: RX CH2 ETM config register
  • IN_ETM_CONF_CH3
    IN_ETM_CONF_CH3 (rw) register accessor: RX CH3 ETM config register
  • IN_ETM_CONF_CH4
    IN_ETM_CONF_CH4 (rw) register accessor: RX CH4 ETM config register
  • IN_FIFO_CNT_CH0
    IN_FIFO_CNT_CH0 (r) register accessor: rx CH0 fifo cnt register
  • IN_FIFO_CNT_CH1
    IN_FIFO_CNT_CH1 (r) register accessor: rx CH1 fifo cnt register
  • IN_FIFO_CNT_CH2
    IN_FIFO_CNT_CH2 (r) register accessor: rx CH2 fifo cnt register
  • IN_FIFO_CNT_CH3
    IN_FIFO_CNT_CH3 (r) register accessor: rx CH3 fifo cnt register
  • IN_FIFO_CNT_CH4
    IN_FIFO_CNT_CH4 (r) register accessor: rx CH4 fifo cnt register
  • IN_FIFO_CNT_CH5
    IN_FIFO_CNT_CH5 (r) register accessor: rx CH5 fifo cnt register
  • IN_INT_CLR_CH0
    IN_INT_CLR_CH0 (w) register accessor: RX CH0 interrupt clr register
  • IN_INT_CLR_CH1
    IN_INT_CLR_CH1 (w) register accessor: RX CH1 interrupt clr register
  • IN_INT_CLR_CH2
    IN_INT_CLR_CH2 (w) register accessor: RX CH2 interrupt clr register
  • IN_INT_CLR_CH3
    IN_INT_CLR_CH3 (w) register accessor: RX CH3 interrupt clr register
  • IN_INT_CLR_CH4
    IN_INT_CLR_CH4 (w) register accessor: RX CH4 interrupt clr register
  • IN_INT_CLR_CH5
    IN_INT_CLR_CH5 (w) register accessor: RX CH5 interrupt clr register
  • IN_INT_ENA_CH0
    IN_INT_ENA_CH0 (rw) register accessor: RX CH0 interrupt ena register
  • IN_INT_ENA_CH1
    IN_INT_ENA_CH1 (rw) register accessor: RX CH1 interrupt ena register
  • IN_INT_ENA_CH2
    IN_INT_ENA_CH2 (rw) register accessor: RX CH2 interrupt ena register
  • IN_INT_ENA_CH3
    IN_INT_ENA_CH3 (rw) register accessor: RX CH3 interrupt ena register
  • IN_INT_ENA_CH4
    IN_INT_ENA_CH4 (rw) register accessor: RX CH4 interrupt ena register
  • IN_INT_ENA_CH5
    IN_INT_ENA_CH5 (rw) register accessor: RX CH5 interrupt ena register
  • IN_INT_RAW_CH0
    IN_INT_RAW_CH0 (rw) register accessor: RX CH0 interrupt raw register
  • IN_INT_RAW_CH1
    IN_INT_RAW_CH1 (rw) register accessor: RX CH1 interrupt raw register
  • IN_INT_RAW_CH2
    IN_INT_RAW_CH2 (rw) register accessor: RX CH2 interrupt raw register
  • IN_INT_RAW_CH3
    IN_INT_RAW_CH3 (rw) register accessor: RX CH3 interrupt raw register
  • IN_INT_RAW_CH4
    IN_INT_RAW_CH4 (rw) register accessor: RX CH4 interrupt raw register
  • IN_INT_RAW_CH5
    IN_INT_RAW_CH5 (rw) register accessor: RX CH5 interrupt raw register
  • IN_INT_ST_CH0
    IN_INT_ST_CH0 (r) register accessor: RX CH0 interrupt st register
  • IN_INT_ST_CH1
    IN_INT_ST_CH1 (r) register accessor: RX CH1 interrupt st register
  • IN_INT_ST_CH2
    IN_INT_ST_CH2 (r) register accessor: RX CH2 interrupt st register
  • IN_INT_ST_CH3
    IN_INT_ST_CH3 (r) register accessor: RX CH3 interrupt st register
  • IN_INT_ST_CH4
    IN_INT_ST_CH4 (r) register accessor: RX CH4 interrupt st register
  • IN_INT_ST_CH5
    IN_INT_ST_CH5 (r) register accessor: RX CH5 interrupt st register
  • IN_LINK_ADDR_CH0
    IN_LINK_ADDR_CH0 (rw) register accessor: RX CH0 in_link dscr addr register
  • IN_LINK_ADDR_CH1
    IN_LINK_ADDR_CH1 (rw) register accessor: RX CH1 in_link dscr addr register
  • IN_LINK_ADDR_CH2
    IN_LINK_ADDR_CH2 (rw) register accessor: RX CH2 in_link dscr addr register
  • IN_LINK_ADDR_CH3
    IN_LINK_ADDR_CH3 (rw) register accessor: RX CH3 in_link dscr addr register
  • IN_LINK_ADDR_CH4
    IN_LINK_ADDR_CH4 (rw) register accessor: RX CH4 in_link dscr addr register
  • IN_LINK_CONF_CH0
    IN_LINK_CONF_CH0 (rw) register accessor: RX CH0 in_link dscr ctrl register
  • IN_LINK_CONF_CH1
    IN_LINK_CONF_CH1 (rw) register accessor: RX CH1 in_link dscr ctrl register
  • IN_LINK_CONF_CH2
    IN_LINK_CONF_CH2 (rw) register accessor: RX CH2 in_link dscr ctrl register
  • IN_LINK_CONF_CH3
    IN_LINK_CONF_CH3 (rw) register accessor: RX CH3 in_link dscr ctrl register
  • IN_LINK_CONF_CH4
    IN_LINK_CONF_CH4 (rw) register accessor: RX CH4 in_link dscr ctrl register
  • IN_POP_CH0
    IN_POP_CH0 (rw) register accessor: RX CH0 INFIFO pop register
  • IN_POP_CH1
    IN_POP_CH1 (rw) register accessor: RX CH1 INFIFO pop register
  • IN_POP_CH2
    IN_POP_CH2 (rw) register accessor: RX CH2 INFIFO pop register
  • IN_POP_CH3
    IN_POP_CH3 (rw) register accessor: RX CH3 INFIFO pop register
  • IN_POP_CH4
    IN_POP_CH4 (rw) register accessor: RX CH4 INFIFO pop register
  • IN_POP_CH5
    IN_POP_CH5 (rw) register accessor: RX CH5 INFIFO pop register
  • IN_POP_DATA_CNT_CH0
    IN_POP_DATA_CNT_CH0 (r) register accessor: rx CH0 pop data cnt register
  • IN_POP_DATA_CNT_CH1
    IN_POP_DATA_CNT_CH1 (r) register accessor: rx CH1 pop data cnt register
  • IN_POP_DATA_CNT_CH2
    IN_POP_DATA_CNT_CH2 (r) register accessor: rx CH2 pop data cnt register
  • IN_POP_DATA_CNT_CH3
    IN_POP_DATA_CNT_CH3 (r) register accessor: rx CH3 pop data cnt register
  • IN_POP_DATA_CNT_CH4
    IN_POP_DATA_CNT_CH4 (r) register accessor: rx CH4 pop data cnt register
  • IN_POP_DATA_CNT_CH5
    IN_POP_DATA_CNT_CH5 (r) register accessor: rx CH5 pop data cnt register
  • IN_RO_PD_CONF_CH0
    IN_RO_PD_CONF_CH0 (rw) register accessor: RX CH0 reorder power config register
  • IN_STATE_CH0
    IN_STATE_CH0 (r) register accessor: RX CH0 state register
  • IN_STATE_CH1
    IN_STATE_CH1 (r) register accessor: RX CH1 state register
  • IN_STATE_CH2
    IN_STATE_CH2 (r) register accessor: RX CH2 state register
  • IN_STATE_CH3
    IN_STATE_CH3 (r) register accessor: RX CH3 state register
  • IN_STATE_CH4
    IN_STATE_CH4 (r) register accessor: RX CH4 state register
  • IN_STATE_CH5
    IN_STATE_CH5 (r) register accessor: RX CH5 state register
  • IN_SUC_EOF_DES_ADDR_CH0
    IN_SUC_EOF_DES_ADDR_CH0 (r) register accessor: RX CH0 eof des addr register
  • IN_SUC_EOF_DES_ADDR_CH1
    IN_SUC_EOF_DES_ADDR_CH1 (r) register accessor: RX CH1 eof des addr register
  • IN_SUC_EOF_DES_ADDR_CH2
    IN_SUC_EOF_DES_ADDR_CH2 (r) register accessor: RX CH2 eof des addr register
  • IN_SUC_EOF_DES_ADDR_CH3
    IN_SUC_EOF_DES_ADDR_CH3 (r) register accessor: RX CH3 eof des addr register
  • IN_SUC_EOF_DES_ADDR_CH4
    IN_SUC_EOF_DES_ADDR_CH4 (r) register accessor: RX CH4 eof des addr register
  • IN_XADDR_CH0
    IN_XADDR_CH0 (r) register accessor: rx CH0 xaddr register
  • IN_XADDR_CH1
    IN_XADDR_CH1 (r) register accessor: rx CH1 xaddr register
  • IN_XADDR_CH2
    IN_XADDR_CH2 (r) register accessor: rx CH2 xaddr register
  • IN_XADDR_CH3
    IN_XADDR_CH3 (r) register accessor: rx CH3 xaddr register
  • IN_XADDR_CH4
    IN_XADDR_CH4 (r) register accessor: rx CH4 xaddr register
  • IN_XADDR_CH5
    IN_XADDR_CH5 (r) register accessor: rx CH5 xaddr register
  • OUTFIFO_STATUS_CH0
    OUTFIFO_STATUS_CH0 (r) register accessor: TX CH0 outfifo status register
  • OUTFIFO_STATUS_CH1
    OUTFIFO_STATUS_CH1 (r) register accessor: TX CH1 outfifo status register
  • OUTFIFO_STATUS_CH2
    OUTFIFO_STATUS_CH2 (r) register accessor: TX CH2 outfifo status register
  • OUTFIFO_STATUS_CH3
    OUTFIFO_STATUS_CH3 (r) register accessor: TX CH3 outfifo status register
  • OUTFIFO_STATUS_CH4
    OUTFIFO_STATUS_CH4 (r) register accessor: TX CH4 outfifo status register
  • OUT_ARB_CH0
    OUT_ARB_CH0 (rw) register accessor: TX CH0 arb register
  • OUT_ARB_CH1
    OUT_ARB_CH1 (rw) register accessor: TX CH1 arb register
  • OUT_ARB_CH2
    OUT_ARB_CH2 (rw) register accessor: TX CH2 arb register
  • OUT_ARB_CH3
    OUT_ARB_CH3 (rw) register accessor: TX CH3 arb register
  • OUT_ARB_CH4
    OUT_ARB_CH4 (rw) register accessor: TX CH4 arb register
  • OUT_ARB_CONFIG
    OUT_ARB_CONFIG (rw) register accessor: reserved
  • OUT_BLOCK_BUF_LEN_CH3
    OUT_BLOCK_BUF_LEN_CH3 (r) register accessor: tx CH3 block buf len register
  • OUT_BLOCK_BUF_LEN_CH4
    OUT_BLOCK_BUF_LEN_CH4 (r) register accessor: tx CH4 block buf len register
  • OUT_BUF_LEN_CH0
    OUT_BUF_LEN_CH0 (r) register accessor: tx CH0 buf len register
  • OUT_BUF_LEN_CH1
    OUT_BUF_LEN_CH1 (r) register accessor: tx CH1 buf len register
  • OUT_BUF_LEN_CH2
    OUT_BUF_LEN_CH2 (r) register accessor: tx CH2 buf len register
  • OUT_BUF_LEN_CH3
    OUT_BUF_LEN_CH3 (r) register accessor: tx CH3 buf len register
  • OUT_BUF_LEN_CH4
    OUT_BUF_LEN_CH4 (r) register accessor: tx CH4 buf len register
  • OUT_CONF0_CH0
    OUT_CONF0_CH0 (rw) register accessor: TX CH0 config0 register
  • OUT_CONF0_CH1
    OUT_CONF0_CH1 (rw) register accessor: TX CH1 config0 register
  • OUT_CONF0_CH2
    OUT_CONF0_CH2 (rw) register accessor: TX CH2 config0 register
  • OUT_CONF0_CH3
    OUT_CONF0_CH3 (rw) register accessor: TX CH3 config0 register
  • OUT_CONF0_CH4
    OUT_CONF0_CH4 (rw) register accessor: TX CH4 config0 register
  • OUT_DSCR_BF0_CH0
    OUT_DSCR_BF0_CH0 (r) register accessor: TX CH0 last dscr addr register
  • OUT_DSCR_BF0_CH1
    OUT_DSCR_BF0_CH1 (r) register accessor: TX CH1 last dscr addr register
  • OUT_DSCR_BF0_CH2
    OUT_DSCR_BF0_CH2 (r) register accessor: TX CH2 last dscr addr register
  • OUT_DSCR_BF0_CH3
    OUT_DSCR_BF0_CH3 (r) register accessor: TX CH3 last dscr addr register
  • OUT_DSCR_BF0_CH4
    OUT_DSCR_BF0_CH4 (r) register accessor: TX CH4 last dscr addr register
  • OUT_DSCR_BF1_CH0
    OUT_DSCR_BF1_CH0 (r) register accessor: TX CH0 second-to-last dscr addr register
  • OUT_DSCR_BF1_CH1
    OUT_DSCR_BF1_CH1 (r) register accessor: TX CH1 second-to-last dscr addr register
  • OUT_DSCR_BF1_CH2
    OUT_DSCR_BF1_CH2 (r) register accessor: TX CH2 second-to-last dscr addr register
  • OUT_DSCR_BF1_CH3
    OUT_DSCR_BF1_CH3 (r) register accessor: TX CH3 second-to-last dscr addr register
  • OUT_DSCR_BF1_CH4
    OUT_DSCR_BF1_CH4 (r) register accessor: TX CH4 second-to-last dscr addr register
  • OUT_DSCR_CH0
    OUT_DSCR_CH0 (r) register accessor: TX CH0 next dscr addr register
  • OUT_DSCR_CH1
    OUT_DSCR_CH1 (r) register accessor: TX CH1 next dscr addr register
  • OUT_DSCR_CH2
    OUT_DSCR_CH2 (r) register accessor: TX CH2 next dscr addr register
  • OUT_DSCR_CH3
    OUT_DSCR_CH3 (r) register accessor: TX CH3 next dscr addr register
  • OUT_DSCR_CH4
    OUT_DSCR_CH4 (r) register accessor: TX CH4 next dscr addr register
  • OUT_EOF_DES_ADDR_CH0
    OUT_EOF_DES_ADDR_CH0 (r) register accessor: TX CH0 eof des addr register
  • OUT_EOF_DES_ADDR_CH1
    OUT_EOF_DES_ADDR_CH1 (r) register accessor: TX CH1 eof des addr register
  • OUT_EOF_DES_ADDR_CH2
    OUT_EOF_DES_ADDR_CH2 (r) register accessor: TX CH2 eof des addr register
  • OUT_EOF_DES_ADDR_CH3
    OUT_EOF_DES_ADDR_CH3 (r) register accessor: TX CH3 eof des addr register
  • OUT_EOF_DES_ADDR_CH4
    OUT_EOF_DES_ADDR_CH4 (r) register accessor: TX CH4 eof des addr register
  • OUT_ETM_CONF_CH0
    OUT_ETM_CONF_CH0 (rw) register accessor: TX CH0 ETM config register
  • OUT_ETM_CONF_CH1
    OUT_ETM_CONF_CH1 (rw) register accessor: TX CH1 ETM config register
  • OUT_ETM_CONF_CH2
    OUT_ETM_CONF_CH2 (rw) register accessor: TX CH2 ETM config register
  • OUT_ETM_CONF_CH3
    OUT_ETM_CONF_CH3 (rw) register accessor: TX CH3 ETM config register
  • OUT_ETM_CONF_CH4
    OUT_ETM_CONF_CH4 (rw) register accessor: TX CH4 ETM config register
  • OUT_FIFO_BCNT_CH0
    OUT_FIFO_BCNT_CH0 (r) register accessor: tx CH0 fifo byte cnt register
  • OUT_FIFO_BCNT_CH1
    OUT_FIFO_BCNT_CH1 (r) register accessor: tx CH1 fifo byte cnt register
  • OUT_FIFO_BCNT_CH2
    OUT_FIFO_BCNT_CH2 (r) register accessor: tx CH2 fifo byte cnt register
  • OUT_FIFO_BCNT_CH3
    OUT_FIFO_BCNT_CH3 (r) register accessor: tx CH3 fifo byte cnt register
  • OUT_FIFO_BCNT_CH4
    OUT_FIFO_BCNT_CH4 (r) register accessor: tx CH4 fifo byte cnt register
  • OUT_INT_CLR_CH0
    OUT_INT_CLR_CH0 (w) register accessor: TX CH0 interrupt clr register
  • OUT_INT_CLR_CH1
    OUT_INT_CLR_CH1 (w) register accessor: TX CH1 interrupt clr register
  • OUT_INT_CLR_CH2
    OUT_INT_CLR_CH2 (w) register accessor: TX CH2 interrupt clr register
  • OUT_INT_CLR_CH3
    OUT_INT_CLR_CH3 (w) register accessor: TX CH3 interrupt clr register
  • OUT_INT_CLR_CH4
    OUT_INT_CLR_CH4 (w) register accessor: TX CH4 interrupt clr register
  • OUT_INT_ENA_CH0
    OUT_INT_ENA_CH0 (rw) register accessor: TX CH0 interrupt ena register
  • OUT_INT_ENA_CH1
    OUT_INT_ENA_CH1 (rw) register accessor: TX CH1 interrupt ena register
  • OUT_INT_ENA_CH2
    OUT_INT_ENA_CH2 (rw) register accessor: TX CH2 interrupt ena register
  • OUT_INT_ENA_CH3
    OUT_INT_ENA_CH3 (rw) register accessor: TX CH3 interrupt ena register
  • OUT_INT_ENA_CH4
    OUT_INT_ENA_CH4 (rw) register accessor: TX CH4 interrupt ena register
  • OUT_INT_RAW_CH0
    OUT_INT_RAW_CH0 (rw) register accessor: TX CH0 interrupt raw register
  • OUT_INT_RAW_CH1
    OUT_INT_RAW_CH1 (rw) register accessor: TX CH1 interrupt raw register
  • OUT_INT_RAW_CH2
    OUT_INT_RAW_CH2 (rw) register accessor: TX CH2 interrupt raw register
  • OUT_INT_RAW_CH3
    OUT_INT_RAW_CH3 (rw) register accessor: TX CH3 interrupt raw register
  • OUT_INT_RAW_CH4
    OUT_INT_RAW_CH4 (rw) register accessor: TX CH4 interrupt raw register
  • OUT_INT_ST_CH0
    OUT_INT_ST_CH0 (r) register accessor: TX CH0 interrupt st register
  • OUT_INT_ST_CH1
    OUT_INT_ST_CH1 (r) register accessor: TX CH1 interrupt st register
  • OUT_INT_ST_CH2
    OUT_INT_ST_CH2 (r) register accessor: TX CH2 interrupt st register
  • OUT_INT_ST_CH3
    OUT_INT_ST_CH3 (r) register accessor: TX CH3 interrupt st register
  • OUT_INT_ST_CH4
    OUT_INT_ST_CH4 (r) register accessor: TX CH4 interrupt st register
  • OUT_LINK_ADDR_CH0
    OUT_LINK_ADDR_CH0 (rw) register accessor: TX CH0 out_link dscr addr register
  • OUT_LINK_ADDR_CH1
    OUT_LINK_ADDR_CH1 (rw) register accessor: TX CH1 out_link dscr addr register
  • OUT_LINK_ADDR_CH2
    OUT_LINK_ADDR_CH2 (rw) register accessor: TX CH2 out_link dscr addr register
  • OUT_LINK_ADDR_CH3
    OUT_LINK_ADDR_CH3 (rw) register accessor: TX CH3 out_link dscr addr register
  • OUT_LINK_ADDR_CH4
    OUT_LINK_ADDR_CH4 (rw) register accessor: TX CH4 out_link dscr addr register
  • OUT_LINK_CONF_CH0
    OUT_LINK_CONF_CH0 (rw) register accessor: TX CH0 out_link dscr ctrl register
  • OUT_LINK_CONF_CH1
    OUT_LINK_CONF_CH1 (rw) register accessor: TX CH1 out_link dscr ctrl register
  • OUT_LINK_CONF_CH2
    OUT_LINK_CONF_CH2 (rw) register accessor: TX CH2 out_link dscr ctrl register
  • OUT_LINK_CONF_CH3
    OUT_LINK_CONF_CH3 (rw) register accessor: TX CH3 out_link dscr ctrl register
  • OUT_LINK_CONF_CH4
    OUT_LINK_CONF_CH4 (rw) register accessor: TX CH4 out_link dscr ctrl register
  • OUT_MODE_ENABLE_CH0
    OUT_MODE_ENABLE_CH0 (rw) register accessor: tx CH0 mode enable register
  • OUT_MODE_YUV_CH0
    OUT_MODE_YUV_CH0 (rw) register accessor: tx CH0 test mode yuv value register
  • OUT_PUSH_BYTECNT_CH0
    OUT_PUSH_BYTECNT_CH0 (r) register accessor: tx CH0 push byte cnt register
  • OUT_PUSH_BYTECNT_CH1
    OUT_PUSH_BYTECNT_CH1 (r) register accessor: tx CH1 push byte cnt register
  • OUT_PUSH_BYTECNT_CH2
    OUT_PUSH_BYTECNT_CH2 (r) register accessor: tx CH2 push byte cnt register
  • OUT_PUSH_BYTECNT_CH3
    OUT_PUSH_BYTECNT_CH3 (r) register accessor: tx CH3 push byte cnt register
  • OUT_PUSH_BYTECNT_CH4
    OUT_PUSH_BYTECNT_CH4 (r) register accessor: tx CH4 push byte cnt register
  • OUT_PUSH_CH0
    OUT_PUSH_CH0 (rw) register accessor: TX CH0 outfifo push register
  • OUT_PUSH_CH1
    OUT_PUSH_CH1 (rw) register accessor: TX CH1 outfifo push register
  • OUT_PUSH_CH2
    OUT_PUSH_CH2 (rw) register accessor: TX CH2 outfifo push register
  • OUT_PUSH_CH3
    OUT_PUSH_CH3 (rw) register accessor: TX CH3 outfifo push register
  • OUT_PUSH_CH4
    OUT_PUSH_CH4 (rw) register accessor: TX CH4 outfifo push register
  • OUT_RO_PD_CONF_CH0
    OUT_RO_PD_CONF_CH0 (rw) register accessor: TX CH0 reorder power config register
  • OUT_RO_STATUS_CH0
    OUT_RO_STATUS_CH0 (r) register accessor: TX CH0 reorder status register
  • OUT_STATE_CH0
    OUT_STATE_CH0 (r) register accessor: TX CH0 state register
  • OUT_STATE_CH1
    OUT_STATE_CH1 (r) register accessor: TX CH1 state register
  • OUT_STATE_CH2
    OUT_STATE_CH2 (r) register accessor: TX CH2 state register
  • OUT_STATE_CH3
    OUT_STATE_CH3 (r) register accessor: TX CH3 state register
  • OUT_STATE_CH4
    OUT_STATE_CH4 (r) register accessor: TX CH4 state register
  • OUT_XADDR_CH0
    OUT_XADDR_CH0 (r) register accessor: tx CH0 xaddr register
  • OUT_XADDR_CH1
    OUT_XADDR_CH1 (r) register accessor: tx CH1 xaddr register
  • OUT_XADDR_CH2
    OUT_XADDR_CH2 (r) register accessor: tx CH2 xaddr register
  • OUT_XADDR_CH3
    OUT_XADDR_CH3 (r) register accessor: tx CH3 xaddr register
  • OUT_XADDR_CH4
    OUT_XADDR_CH4 (r) register accessor: tx CH4 xaddr register
  • RST_CONF
    RST_CONF (rw) register accessor: axi reset config register
  • RX_CH0_COUNTER
    RX_CH0_COUNTER (r) register accessor: rx ch0 counter register
  • RX_CH1_COUNTER
    RX_CH1_COUNTER (r) register accessor: rx ch1 counter register
  • RX_CH2_COUNTER
    RX_CH2_COUNTER (r) register accessor: rx ch2 counter register
  • RX_CH5_COUNTER
    RX_CH5_COUNTER (r) register accessor: rx ch5 counter register