esp32h2/interrupt_core0/
cache_intr_map.rs

1#[doc = "Register `CACHE_INTR_MAP` reader"]
2pub type R = crate::R<CACHE_INTR_MAP_SPEC>;
3#[doc = "Register `CACHE_INTR_MAP` writer"]
4pub type W = crate::W<CACHE_INTR_MAP_SPEC>;
5#[doc = "Field `CACHE_INTR_MAP` reader - CORE0_CACHE_INTR mapping register"]
6pub type CACHE_INTR_MAP_R = crate::FieldReader;
7#[doc = "Field `CACHE_INTR_MAP` writer - CORE0_CACHE_INTR mapping register"]
8pub type CACHE_INTR_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9impl R {
10    #[doc = "Bits 0:4 - CORE0_CACHE_INTR mapping register"]
11    #[inline(always)]
12    pub fn cache_intr_map(&self) -> CACHE_INTR_MAP_R {
13        CACHE_INTR_MAP_R::new((self.bits & 0x1f) as u8)
14    }
15}
16#[cfg(feature = "impl-register-debug")]
17impl core::fmt::Debug for R {
18    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19        f.debug_struct("CACHE_INTR_MAP")
20            .field("cache_intr_map", &self.cache_intr_map())
21            .finish()
22    }
23}
24impl W {
25    #[doc = "Bits 0:4 - CORE0_CACHE_INTR mapping register"]
26    #[inline(always)]
27    pub fn cache_intr_map(&mut self) -> CACHE_INTR_MAP_W<CACHE_INTR_MAP_SPEC> {
28        CACHE_INTR_MAP_W::new(self, 0)
29    }
30}
31#[doc = "register description\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_intr_map::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_intr_map::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
32pub struct CACHE_INTR_MAP_SPEC;
33impl crate::RegisterSpec for CACHE_INTR_MAP_SPEC {
34    type Ux = u32;
35}
36#[doc = "`read()` method returns [`cache_intr_map::R`](R) reader structure"]
37impl crate::Readable for CACHE_INTR_MAP_SPEC {}
38#[doc = "`write(|w| ..)` method takes [`cache_intr_map::W`](W) writer structure"]
39impl crate::Writable for CACHE_INTR_MAP_SPEC {
40    type Safety = crate::Unsafe;
41    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
42    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
43}
44#[doc = "`reset()` method sets CACHE_INTR_MAP to value 0"]
45impl crate::Resettable for CACHE_INTR_MAP_SPEC {
46    const RESET_VALUE: u32 = 0;
47}
esp32h2/interrupt_core0/cache_intr_map.rs

esp32h2/interrupt_core0/
cache_intr_map.rs
