1#[doc = "Register `CONF0` reader"]
2pub type R = crate::R<CONF0_SPEC>;
3#[doc = "Register `CONF0` writer"]
4pub type W = crate::W<CONF0_SPEC>;
5#[doc = "Field `PARITY` reader - This register is used to configure the parity check mode."]
6pub type PARITY_R = crate::BitReader;
7#[doc = "Field `PARITY` writer - This register is used to configure the parity check mode."]
8pub type PARITY_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `PARITY_EN` reader - Set this bit to enable uart parity check."]
10pub type PARITY_EN_R = crate::BitReader;
11#[doc = "Field `PARITY_EN` writer - Set this bit to enable uart parity check."]
12pub type PARITY_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `BIT_NUM` reader - This register is used to set the length of data."]
14pub type BIT_NUM_R = crate::FieldReader;
15#[doc = "Field `BIT_NUM` writer - This register is used to set the length of data."]
16pub type BIT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17#[doc = "Field `STOP_BIT_NUM` reader - This register is used to set the length of stop bit."]
18pub type STOP_BIT_NUM_R = crate::FieldReader;
19#[doc = "Field `STOP_BIT_NUM` writer - This register is used to set the length of stop bit."]
20pub type STOP_BIT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21#[doc = "Field `TXD_BRK` reader - Set this bit to enbale transmitter to send NULL when the process of sending data is done."]
22pub type TXD_BRK_R = crate::BitReader;
23#[doc = "Field `TXD_BRK` writer - Set this bit to enbale transmitter to send NULL when the process of sending data is done."]
24pub type TXD_BRK_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `IRDA_DPLX` reader - Set this bit to enable IrDA loopback mode."]
26pub type IRDA_DPLX_R = crate::BitReader;
27#[doc = "Field `IRDA_DPLX` writer - Set this bit to enable IrDA loopback mode."]
28pub type IRDA_DPLX_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `IRDA_TX_EN` reader - This is the start enable bit for IrDA transmitter."]
30pub type IRDA_TX_EN_R = crate::BitReader;
31#[doc = "Field `IRDA_TX_EN` writer - This is the start enable bit for IrDA transmitter."]
32pub type IRDA_TX_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `IRDA_WCTL` reader - 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0."]
34pub type IRDA_WCTL_R = crate::BitReader;
35#[doc = "Field `IRDA_WCTL` writer - 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0."]
36pub type IRDA_WCTL_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `IRDA_TX_INV` reader - Set this bit to invert the level of IrDA transmitter."]
38pub type IRDA_TX_INV_R = crate::BitReader;
39#[doc = "Field `IRDA_TX_INV` writer - Set this bit to invert the level of IrDA transmitter."]
40pub type IRDA_TX_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `IRDA_RX_INV` reader - Set this bit to invert the level of IrDA receiver."]
42pub type IRDA_RX_INV_R = crate::BitReader;
43#[doc = "Field `IRDA_RX_INV` writer - Set this bit to invert the level of IrDA receiver."]
44pub type IRDA_RX_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `LOOPBACK` reader - Set this bit to enable uart loopback test mode."]
46pub type LOOPBACK_R = crate::BitReader;
47#[doc = "Field `LOOPBACK` writer - Set this bit to enable uart loopback test mode."]
48pub type LOOPBACK_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `TX_FLOW_EN` reader - Set this bit to enable flow control function for transmitter."]
50pub type TX_FLOW_EN_R = crate::BitReader;
51#[doc = "Field `TX_FLOW_EN` writer - Set this bit to enable flow control function for transmitter."]
52pub type TX_FLOW_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `IRDA_EN` reader - Set this bit to enable IrDA protocol."]
54pub type IRDA_EN_R = crate::BitReader;
55#[doc = "Field `IRDA_EN` writer - Set this bit to enable IrDA protocol."]
56pub type IRDA_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `RXD_INV` reader - Set this bit to inverse the level value of uart rxd signal."]
58pub type RXD_INV_R = crate::BitReader;
59#[doc = "Field `RXD_INV` writer - Set this bit to inverse the level value of uart rxd signal."]
60pub type RXD_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `TXD_INV` reader - Set this bit to inverse the level value of uart txd signal."]
62pub type TXD_INV_R = crate::BitReader;
63#[doc = "Field `TXD_INV` writer - Set this bit to inverse the level value of uart txd signal."]
64pub type TXD_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `DIS_RX_DAT_OVF` reader - Disable UART Rx data overflow detect."]
66pub type DIS_RX_DAT_OVF_R = crate::BitReader;
67#[doc = "Field `DIS_RX_DAT_OVF` writer - Disable UART Rx data overflow detect."]
68pub type DIS_RX_DAT_OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `ERR_WR_MASK` reader - 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong."]
70pub type ERR_WR_MASK_R = crate::BitReader;
71#[doc = "Field `ERR_WR_MASK` writer - 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong."]
72pub type ERR_WR_MASK_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `AUTOBAUD_EN` reader - This is the enable bit for detecting baudrate."]
74pub type AUTOBAUD_EN_R = crate::BitReader;
75#[doc = "Field `AUTOBAUD_EN` writer - This is the enable bit for detecting baudrate."]
76pub type AUTOBAUD_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `MEM_CLK_EN` reader - UART memory clock gate enable signal."]
78pub type MEM_CLK_EN_R = crate::BitReader;
79#[doc = "Field `MEM_CLK_EN` writer - UART memory clock gate enable signal."]
80pub type MEM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
81#[doc = "Field `SW_RTS` reader - This register is used to configure the software rts signal which is used in software flow control."]
82pub type SW_RTS_R = crate::BitReader;
83#[doc = "Field `SW_RTS` writer - This register is used to configure the software rts signal which is used in software flow control."]
84pub type SW_RTS_W<'a, REG> = crate::BitWriter<'a, REG>;
85#[doc = "Field `RXFIFO_RST` reader - Set this bit to reset the uart receive-FIFO."]
86pub type RXFIFO_RST_R = crate::BitReader;
87#[doc = "Field `RXFIFO_RST` writer - Set this bit to reset the uart receive-FIFO."]
88pub type RXFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
89#[doc = "Field `TXFIFO_RST` reader - Set this bit to reset the uart transmit-FIFO."]
90pub type TXFIFO_RST_R = crate::BitReader;
91#[doc = "Field `TXFIFO_RST` writer - Set this bit to reset the uart transmit-FIFO."]
92pub type TXFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
93impl R {
94 #[doc = "Bit 0 - This register is used to configure the parity check mode."]
95 #[inline(always)]
96 pub fn parity(&self) -> PARITY_R {
97 PARITY_R::new((self.bits & 1) != 0)
98 }
99 #[doc = "Bit 1 - Set this bit to enable uart parity check."]
100 #[inline(always)]
101 pub fn parity_en(&self) -> PARITY_EN_R {
102 PARITY_EN_R::new(((self.bits >> 1) & 1) != 0)
103 }
104 #[doc = "Bits 2:3 - This register is used to set the length of data."]
105 #[inline(always)]
106 pub fn bit_num(&self) -> BIT_NUM_R {
107 BIT_NUM_R::new(((self.bits >> 2) & 3) as u8)
108 }
109 #[doc = "Bits 4:5 - This register is used to set the length of stop bit."]
110 #[inline(always)]
111 pub fn stop_bit_num(&self) -> STOP_BIT_NUM_R {
112 STOP_BIT_NUM_R::new(((self.bits >> 4) & 3) as u8)
113 }
114 #[doc = "Bit 6 - Set this bit to enbale transmitter to send NULL when the process of sending data is done."]
115 #[inline(always)]
116 pub fn txd_brk(&self) -> TXD_BRK_R {
117 TXD_BRK_R::new(((self.bits >> 6) & 1) != 0)
118 }
119 #[doc = "Bit 7 - Set this bit to enable IrDA loopback mode."]
120 #[inline(always)]
121 pub fn irda_dplx(&self) -> IRDA_DPLX_R {
122 IRDA_DPLX_R::new(((self.bits >> 7) & 1) != 0)
123 }
124 #[doc = "Bit 8 - This is the start enable bit for IrDA transmitter."]
125 #[inline(always)]
126 pub fn irda_tx_en(&self) -> IRDA_TX_EN_R {
127 IRDA_TX_EN_R::new(((self.bits >> 8) & 1) != 0)
128 }
129 #[doc = "Bit 9 - 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0."]
130 #[inline(always)]
131 pub fn irda_wctl(&self) -> IRDA_WCTL_R {
132 IRDA_WCTL_R::new(((self.bits >> 9) & 1) != 0)
133 }
134 #[doc = "Bit 10 - Set this bit to invert the level of IrDA transmitter."]
135 #[inline(always)]
136 pub fn irda_tx_inv(&self) -> IRDA_TX_INV_R {
137 IRDA_TX_INV_R::new(((self.bits >> 10) & 1) != 0)
138 }
139 #[doc = "Bit 11 - Set this bit to invert the level of IrDA receiver."]
140 #[inline(always)]
141 pub fn irda_rx_inv(&self) -> IRDA_RX_INV_R {
142 IRDA_RX_INV_R::new(((self.bits >> 11) & 1) != 0)
143 }
144 #[doc = "Bit 12 - Set this bit to enable uart loopback test mode."]
145 #[inline(always)]
146 pub fn loopback(&self) -> LOOPBACK_R {
147 LOOPBACK_R::new(((self.bits >> 12) & 1) != 0)
148 }
149 #[doc = "Bit 13 - Set this bit to enable flow control function for transmitter."]
150 #[inline(always)]
151 pub fn tx_flow_en(&self) -> TX_FLOW_EN_R {
152 TX_FLOW_EN_R::new(((self.bits >> 13) & 1) != 0)
153 }
154 #[doc = "Bit 14 - Set this bit to enable IrDA protocol."]
155 #[inline(always)]
156 pub fn irda_en(&self) -> IRDA_EN_R {
157 IRDA_EN_R::new(((self.bits >> 14) & 1) != 0)
158 }
159 #[doc = "Bit 15 - Set this bit to inverse the level value of uart rxd signal."]
160 #[inline(always)]
161 pub fn rxd_inv(&self) -> RXD_INV_R {
162 RXD_INV_R::new(((self.bits >> 15) & 1) != 0)
163 }
164 #[doc = "Bit 16 - Set this bit to inverse the level value of uart txd signal."]
165 #[inline(always)]
166 pub fn txd_inv(&self) -> TXD_INV_R {
167 TXD_INV_R::new(((self.bits >> 16) & 1) != 0)
168 }
169 #[doc = "Bit 17 - Disable UART Rx data overflow detect."]
170 #[inline(always)]
171 pub fn dis_rx_dat_ovf(&self) -> DIS_RX_DAT_OVF_R {
172 DIS_RX_DAT_OVF_R::new(((self.bits >> 17) & 1) != 0)
173 }
174 #[doc = "Bit 18 - 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong."]
175 #[inline(always)]
176 pub fn err_wr_mask(&self) -> ERR_WR_MASK_R {
177 ERR_WR_MASK_R::new(((self.bits >> 18) & 1) != 0)
178 }
179 #[doc = "Bit 19 - This is the enable bit for detecting baudrate."]
180 #[inline(always)]
181 pub fn autobaud_en(&self) -> AUTOBAUD_EN_R {
182 AUTOBAUD_EN_R::new(((self.bits >> 19) & 1) != 0)
183 }
184 #[doc = "Bit 20 - UART memory clock gate enable signal."]
185 #[inline(always)]
186 pub fn mem_clk_en(&self) -> MEM_CLK_EN_R {
187 MEM_CLK_EN_R::new(((self.bits >> 20) & 1) != 0)
188 }
189 #[doc = "Bit 21 - This register is used to configure the software rts signal which is used in software flow control."]
190 #[inline(always)]
191 pub fn sw_rts(&self) -> SW_RTS_R {
192 SW_RTS_R::new(((self.bits >> 21) & 1) != 0)
193 }
194 #[doc = "Bit 22 - Set this bit to reset the uart receive-FIFO."]
195 #[inline(always)]
196 pub fn rxfifo_rst(&self) -> RXFIFO_RST_R {
197 RXFIFO_RST_R::new(((self.bits >> 22) & 1) != 0)
198 }
199 #[doc = "Bit 23 - Set this bit to reset the uart transmit-FIFO."]
200 #[inline(always)]
201 pub fn txfifo_rst(&self) -> TXFIFO_RST_R {
202 TXFIFO_RST_R::new(((self.bits >> 23) & 1) != 0)
203 }
204}
205#[cfg(feature = "impl-register-debug")]
206impl core::fmt::Debug for R {
207 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
208 f.debug_struct("CONF0")
209 .field("parity", &self.parity())
210 .field("parity_en", &self.parity_en())
211 .field("bit_num", &self.bit_num())
212 .field("stop_bit_num", &self.stop_bit_num())
213 .field("txd_brk", &self.txd_brk())
214 .field("irda_dplx", &self.irda_dplx())
215 .field("irda_tx_en", &self.irda_tx_en())
216 .field("irda_wctl", &self.irda_wctl())
217 .field("irda_tx_inv", &self.irda_tx_inv())
218 .field("irda_rx_inv", &self.irda_rx_inv())
219 .field("loopback", &self.loopback())
220 .field("tx_flow_en", &self.tx_flow_en())
221 .field("irda_en", &self.irda_en())
222 .field("rxd_inv", &self.rxd_inv())
223 .field("txd_inv", &self.txd_inv())
224 .field("dis_rx_dat_ovf", &self.dis_rx_dat_ovf())
225 .field("err_wr_mask", &self.err_wr_mask())
226 .field("autobaud_en", &self.autobaud_en())
227 .field("mem_clk_en", &self.mem_clk_en())
228 .field("sw_rts", &self.sw_rts())
229 .field("rxfifo_rst", &self.rxfifo_rst())
230 .field("txfifo_rst", &self.txfifo_rst())
231 .finish()
232 }
233}
234impl W {
235 #[doc = "Bit 0 - This register is used to configure the parity check mode."]
236 #[inline(always)]
237 pub fn parity(&mut self) -> PARITY_W<CONF0_SPEC> {
238 PARITY_W::new(self, 0)
239 }
240 #[doc = "Bit 1 - Set this bit to enable uart parity check."]
241 #[inline(always)]
242 pub fn parity_en(&mut self) -> PARITY_EN_W<CONF0_SPEC> {
243 PARITY_EN_W::new(self, 1)
244 }
245 #[doc = "Bits 2:3 - This register is used to set the length of data."]
246 #[inline(always)]
247 pub fn bit_num(&mut self) -> BIT_NUM_W<CONF0_SPEC> {
248 BIT_NUM_W::new(self, 2)
249 }
250 #[doc = "Bits 4:5 - This register is used to set the length of stop bit."]
251 #[inline(always)]
252 pub fn stop_bit_num(&mut self) -> STOP_BIT_NUM_W<CONF0_SPEC> {
253 STOP_BIT_NUM_W::new(self, 4)
254 }
255 #[doc = "Bit 6 - Set this bit to enbale transmitter to send NULL when the process of sending data is done."]
256 #[inline(always)]
257 pub fn txd_brk(&mut self) -> TXD_BRK_W<CONF0_SPEC> {
258 TXD_BRK_W::new(self, 6)
259 }
260 #[doc = "Bit 7 - Set this bit to enable IrDA loopback mode."]
261 #[inline(always)]
262 pub fn irda_dplx(&mut self) -> IRDA_DPLX_W<CONF0_SPEC> {
263 IRDA_DPLX_W::new(self, 7)
264 }
265 #[doc = "Bit 8 - This is the start enable bit for IrDA transmitter."]
266 #[inline(always)]
267 pub fn irda_tx_en(&mut self) -> IRDA_TX_EN_W<CONF0_SPEC> {
268 IRDA_TX_EN_W::new(self, 8)
269 }
270 #[doc = "Bit 9 - 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0."]
271 #[inline(always)]
272 pub fn irda_wctl(&mut self) -> IRDA_WCTL_W<CONF0_SPEC> {
273 IRDA_WCTL_W::new(self, 9)
274 }
275 #[doc = "Bit 10 - Set this bit to invert the level of IrDA transmitter."]
276 #[inline(always)]
277 pub fn irda_tx_inv(&mut self) -> IRDA_TX_INV_W<CONF0_SPEC> {
278 IRDA_TX_INV_W::new(self, 10)
279 }
280 #[doc = "Bit 11 - Set this bit to invert the level of IrDA receiver."]
281 #[inline(always)]
282 pub fn irda_rx_inv(&mut self) -> IRDA_RX_INV_W<CONF0_SPEC> {
283 IRDA_RX_INV_W::new(self, 11)
284 }
285 #[doc = "Bit 12 - Set this bit to enable uart loopback test mode."]
286 #[inline(always)]
287 pub fn loopback(&mut self) -> LOOPBACK_W<CONF0_SPEC> {
288 LOOPBACK_W::new(self, 12)
289 }
290 #[doc = "Bit 13 - Set this bit to enable flow control function for transmitter."]
291 #[inline(always)]
292 pub fn tx_flow_en(&mut self) -> TX_FLOW_EN_W<CONF0_SPEC> {
293 TX_FLOW_EN_W::new(self, 13)
294 }
295 #[doc = "Bit 14 - Set this bit to enable IrDA protocol."]
296 #[inline(always)]
297 pub fn irda_en(&mut self) -> IRDA_EN_W<CONF0_SPEC> {
298 IRDA_EN_W::new(self, 14)
299 }
300 #[doc = "Bit 15 - Set this bit to inverse the level value of uart rxd signal."]
301 #[inline(always)]
302 pub fn rxd_inv(&mut self) -> RXD_INV_W<CONF0_SPEC> {
303 RXD_INV_W::new(self, 15)
304 }
305 #[doc = "Bit 16 - Set this bit to inverse the level value of uart txd signal."]
306 #[inline(always)]
307 pub fn txd_inv(&mut self) -> TXD_INV_W<CONF0_SPEC> {
308 TXD_INV_W::new(self, 16)
309 }
310 #[doc = "Bit 17 - Disable UART Rx data overflow detect."]
311 #[inline(always)]
312 pub fn dis_rx_dat_ovf(&mut self) -> DIS_RX_DAT_OVF_W<CONF0_SPEC> {
313 DIS_RX_DAT_OVF_W::new(self, 17)
314 }
315 #[doc = "Bit 18 - 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong."]
316 #[inline(always)]
317 pub fn err_wr_mask(&mut self) -> ERR_WR_MASK_W<CONF0_SPEC> {
318 ERR_WR_MASK_W::new(self, 18)
319 }
320 #[doc = "Bit 19 - This is the enable bit for detecting baudrate."]
321 #[inline(always)]
322 pub fn autobaud_en(&mut self) -> AUTOBAUD_EN_W<CONF0_SPEC> {
323 AUTOBAUD_EN_W::new(self, 19)
324 }
325 #[doc = "Bit 20 - UART memory clock gate enable signal."]
326 #[inline(always)]
327 pub fn mem_clk_en(&mut self) -> MEM_CLK_EN_W<CONF0_SPEC> {
328 MEM_CLK_EN_W::new(self, 20)
329 }
330 #[doc = "Bit 21 - This register is used to configure the software rts signal which is used in software flow control."]
331 #[inline(always)]
332 pub fn sw_rts(&mut self) -> SW_RTS_W<CONF0_SPEC> {
333 SW_RTS_W::new(self, 21)
334 }
335 #[doc = "Bit 22 - Set this bit to reset the uart receive-FIFO."]
336 #[inline(always)]
337 pub fn rxfifo_rst(&mut self) -> RXFIFO_RST_W<CONF0_SPEC> {
338 RXFIFO_RST_W::new(self, 22)
339 }
340 #[doc = "Bit 23 - Set this bit to reset the uart transmit-FIFO."]
341 #[inline(always)]
342 pub fn txfifo_rst(&mut self) -> TXFIFO_RST_W<CONF0_SPEC> {
343 TXFIFO_RST_W::new(self, 23)
344 }
345}
346#[doc = "a\n\nYou can [`read`](crate::Reg::read) this register and get [`conf0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
347pub struct CONF0_SPEC;
348impl crate::RegisterSpec for CONF0_SPEC {
349 type Ux = u32;
350}
351#[doc = "`read()` method returns [`conf0::R`](R) reader structure"]
352impl crate::Readable for CONF0_SPEC {}
353#[doc = "`write(|w| ..)` method takes [`conf0::W`](W) writer structure"]
354impl crate::Writable for CONF0_SPEC {
355 type Safety = crate::Unsafe;
356 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
357 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
358}
359#[doc = "`reset()` method sets CONF0 to value 0x0010_001c"]
360impl crate::Resettable for CONF0_SPEC {
361 const RESET_VALUE: u32 = 0x0010_001c;
362}