1#[doc = "Register `INTERRUPT_ENABLE` reader"]
2pub type R = crate::R<INTERRUPT_ENABLE_SPEC>;
3#[doc = "Register `INTERRUPT_ENABLE` writer"]
4pub type W = crate::W<INTERRUPT_ENABLE_SPEC>;
5#[doc = "Field `EXT_RECEIVE_INT_ENA` reader - 1: enabled, when the receive buffer status is 'full' the TWAI controller requests the respective interrupt. 0: disable"]
6pub type EXT_RECEIVE_INT_ENA_R = crate::BitReader;
7#[doc = "Field `EXT_RECEIVE_INT_ENA` writer - 1: enabled, when the receive buffer status is 'full' the TWAI controller requests the respective interrupt. 0: disable"]
8pub type EXT_RECEIVE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `EXT_TRANSMIT_INT_ENA` reader - 1: enabled, when a message has been successfully transmitted or the transmit buffer is accessible again (e.g. after an abort transmission command), the TWAI controller requests the respective interrupt. 0: disable"]
10pub type EXT_TRANSMIT_INT_ENA_R = crate::BitReader;
11#[doc = "Field `EXT_TRANSMIT_INT_ENA` writer - 1: enabled, when a message has been successfully transmitted or the transmit buffer is accessible again (e.g. after an abort transmission command), the TWAI controller requests the respective interrupt. 0: disable"]
12pub type EXT_TRANSMIT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `EXT_ERR_WARNING_INT_ENA` reader - 1: enabled, if the error or bus status change (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable"]
14pub type EXT_ERR_WARNING_INT_ENA_R = crate::BitReader;
15#[doc = "Field `EXT_ERR_WARNING_INT_ENA` writer - 1: enabled, if the error or bus status change (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable"]
16pub type EXT_ERR_WARNING_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `EXT_DATA_OVERRUN_INT_ENA` reader - 1: enabled, if the data overrun status bit is set (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable"]
18pub type EXT_DATA_OVERRUN_INT_ENA_R = crate::BitReader;
19#[doc = "Field `EXT_DATA_OVERRUN_INT_ENA` writer - 1: enabled, if the data overrun status bit is set (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable"]
20pub type EXT_DATA_OVERRUN_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `ERR_PASSIVE_INT_ENA` reader - 1: enabled, if the error status of the TWAI controller changes from error active to error passive or vice versa, the respective interrupt is requested. 0: disable"]
22pub type ERR_PASSIVE_INT_ENA_R = crate::BitReader;
23#[doc = "Field `ERR_PASSIVE_INT_ENA` writer - 1: enabled, if the error status of the TWAI controller changes from error active to error passive or vice versa, the respective interrupt is requested. 0: disable"]
24pub type ERR_PASSIVE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `ARBITRATION_LOST_INT_ENA` reader - 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt is requested. 0: disable"]
26pub type ARBITRATION_LOST_INT_ENA_R = crate::BitReader;
27#[doc = "Field `ARBITRATION_LOST_INT_ENA` writer - 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt is requested. 0: disable"]
28pub type ARBITRATION_LOST_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `BUS_ERR_INT_ENA` reader - 1: enabled, if an bus error has been detected, the TWAI controller requests the respective interrupt. 0: disable"]
30pub type BUS_ERR_INT_ENA_R = crate::BitReader;
31#[doc = "Field `BUS_ERR_INT_ENA` writer - 1: enabled, if an bus error has been detected, the TWAI controller requests the respective interrupt. 0: disable"]
32pub type BUS_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `IDLE_INT_ENA` reader - 1: enabled, if state of TWAI become IDLE, the TWAI controller requests the respective interrupt. 0: disable"]
34pub type IDLE_INT_ENA_R = crate::BitReader;
35impl R {
36 #[doc = "Bit 0 - 1: enabled, when the receive buffer status is 'full' the TWAI controller requests the respective interrupt. 0: disable"]
37 #[inline(always)]
38 pub fn ext_receive_int_ena(&self) -> EXT_RECEIVE_INT_ENA_R {
39 EXT_RECEIVE_INT_ENA_R::new((self.bits & 1) != 0)
40 }
41 #[doc = "Bit 1 - 1: enabled, when a message has been successfully transmitted or the transmit buffer is accessible again (e.g. after an abort transmission command), the TWAI controller requests the respective interrupt. 0: disable"]
42 #[inline(always)]
43 pub fn ext_transmit_int_ena(&self) -> EXT_TRANSMIT_INT_ENA_R {
44 EXT_TRANSMIT_INT_ENA_R::new(((self.bits >> 1) & 1) != 0)
45 }
46 #[doc = "Bit 2 - 1: enabled, if the error or bus status change (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable"]
47 #[inline(always)]
48 pub fn ext_err_warning_int_ena(&self) -> EXT_ERR_WARNING_INT_ENA_R {
49 EXT_ERR_WARNING_INT_ENA_R::new(((self.bits >> 2) & 1) != 0)
50 }
51 #[doc = "Bit 3 - 1: enabled, if the data overrun status bit is set (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable"]
52 #[inline(always)]
53 pub fn ext_data_overrun_int_ena(&self) -> EXT_DATA_OVERRUN_INT_ENA_R {
54 EXT_DATA_OVERRUN_INT_ENA_R::new(((self.bits >> 3) & 1) != 0)
55 }
56 #[doc = "Bit 5 - 1: enabled, if the error status of the TWAI controller changes from error active to error passive or vice versa, the respective interrupt is requested. 0: disable"]
57 #[inline(always)]
58 pub fn err_passive_int_ena(&self) -> ERR_PASSIVE_INT_ENA_R {
59 ERR_PASSIVE_INT_ENA_R::new(((self.bits >> 5) & 1) != 0)
60 }
61 #[doc = "Bit 6 - 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt is requested. 0: disable"]
62 #[inline(always)]
63 pub fn arbitration_lost_int_ena(&self) -> ARBITRATION_LOST_INT_ENA_R {
64 ARBITRATION_LOST_INT_ENA_R::new(((self.bits >> 6) & 1) != 0)
65 }
66 #[doc = "Bit 7 - 1: enabled, if an bus error has been detected, the TWAI controller requests the respective interrupt. 0: disable"]
67 #[inline(always)]
68 pub fn bus_err_int_ena(&self) -> BUS_ERR_INT_ENA_R {
69 BUS_ERR_INT_ENA_R::new(((self.bits >> 7) & 1) != 0)
70 }
71 #[doc = "Bit 8 - 1: enabled, if state of TWAI become IDLE, the TWAI controller requests the respective interrupt. 0: disable"]
72 #[inline(always)]
73 pub fn idle_int_ena(&self) -> IDLE_INT_ENA_R {
74 IDLE_INT_ENA_R::new(((self.bits >> 8) & 1) != 0)
75 }
76}
77#[cfg(feature = "impl-register-debug")]
78impl core::fmt::Debug for R {
79 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
80 f.debug_struct("INTERRUPT_ENABLE")
81 .field("ext_receive_int_ena", &self.ext_receive_int_ena())
82 .field("ext_transmit_int_ena", &self.ext_transmit_int_ena())
83 .field("ext_err_warning_int_ena", &self.ext_err_warning_int_ena())
84 .field("ext_data_overrun_int_ena", &self.ext_data_overrun_int_ena())
85 .field("err_passive_int_ena", &self.err_passive_int_ena())
86 .field("arbitration_lost_int_ena", &self.arbitration_lost_int_ena())
87 .field("bus_err_int_ena", &self.bus_err_int_ena())
88 .field("idle_int_ena", &self.idle_int_ena())
89 .finish()
90 }
91}
92impl W {
93 #[doc = "Bit 0 - 1: enabled, when the receive buffer status is 'full' the TWAI controller requests the respective interrupt. 0: disable"]
94 #[inline(always)]
95 pub fn ext_receive_int_ena(&mut self) -> EXT_RECEIVE_INT_ENA_W<INTERRUPT_ENABLE_SPEC> {
96 EXT_RECEIVE_INT_ENA_W::new(self, 0)
97 }
98 #[doc = "Bit 1 - 1: enabled, when a message has been successfully transmitted or the transmit buffer is accessible again (e.g. after an abort transmission command), the TWAI controller requests the respective interrupt. 0: disable"]
99 #[inline(always)]
100 pub fn ext_transmit_int_ena(&mut self) -> EXT_TRANSMIT_INT_ENA_W<INTERRUPT_ENABLE_SPEC> {
101 EXT_TRANSMIT_INT_ENA_W::new(self, 1)
102 }
103 #[doc = "Bit 2 - 1: enabled, if the error or bus status change (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable"]
104 #[inline(always)]
105 pub fn ext_err_warning_int_ena(&mut self) -> EXT_ERR_WARNING_INT_ENA_W<INTERRUPT_ENABLE_SPEC> {
106 EXT_ERR_WARNING_INT_ENA_W::new(self, 2)
107 }
108 #[doc = "Bit 3 - 1: enabled, if the data overrun status bit is set (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable"]
109 #[inline(always)]
110 pub fn ext_data_overrun_int_ena(
111 &mut self,
112 ) -> EXT_DATA_OVERRUN_INT_ENA_W<INTERRUPT_ENABLE_SPEC> {
113 EXT_DATA_OVERRUN_INT_ENA_W::new(self, 3)
114 }
115 #[doc = "Bit 5 - 1: enabled, if the error status of the TWAI controller changes from error active to error passive or vice versa, the respective interrupt is requested. 0: disable"]
116 #[inline(always)]
117 pub fn err_passive_int_ena(&mut self) -> ERR_PASSIVE_INT_ENA_W<INTERRUPT_ENABLE_SPEC> {
118 ERR_PASSIVE_INT_ENA_W::new(self, 5)
119 }
120 #[doc = "Bit 6 - 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt is requested. 0: disable"]
121 #[inline(always)]
122 pub fn arbitration_lost_int_ena(
123 &mut self,
124 ) -> ARBITRATION_LOST_INT_ENA_W<INTERRUPT_ENABLE_SPEC> {
125 ARBITRATION_LOST_INT_ENA_W::new(self, 6)
126 }
127 #[doc = "Bit 7 - 1: enabled, if an bus error has been detected, the TWAI controller requests the respective interrupt. 0: disable"]
128 #[inline(always)]
129 pub fn bus_err_int_ena(&mut self) -> BUS_ERR_INT_ENA_W<INTERRUPT_ENABLE_SPEC> {
130 BUS_ERR_INT_ENA_W::new(self, 7)
131 }
132}
133#[doc = "Interrupt enable register.\n\nYou can [`read`](crate::Reg::read) this register and get [`interrupt_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interrupt_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
134pub struct INTERRUPT_ENABLE_SPEC;
135impl crate::RegisterSpec for INTERRUPT_ENABLE_SPEC {
136 type Ux = u32;
137}
138#[doc = "`read()` method returns [`interrupt_enable::R`](R) reader structure"]
139impl crate::Readable for INTERRUPT_ENABLE_SPEC {}
140#[doc = "`write(|w| ..)` method takes [`interrupt_enable::W`](W) writer structure"]
141impl crate::Writable for INTERRUPT_ENABLE_SPEC {
142 type Safety = crate::Unsafe;
143 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
144 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
145}
146#[doc = "`reset()` method sets INTERRUPT_ENABLE to value 0"]
147impl crate::Resettable for INTERRUPT_ENABLE_SPEC {
148 const RESET_VALUE: u32 = 0;
149}