1#[doc = "Register `DIN_MODE` reader"]
2pub type R = crate::R<DIN_MODE_SPEC>;
3#[doc = "Register `DIN_MODE` writer"]
4pub type W = crate::W<DIN_MODE_SPEC>;
5#[doc = "Field `DIN0_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
6pub type DIN0_MODE_R = crate::FieldReader;
7#[doc = "Field `DIN0_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
8pub type DIN0_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
9#[doc = "Field `DIN1_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
10pub type DIN1_MODE_R = crate::FieldReader;
11#[doc = "Field `DIN1_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
12pub type DIN1_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
13#[doc = "Field `DIN2_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
14pub type DIN2_MODE_R = crate::FieldReader;
15#[doc = "Field `DIN2_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
16pub type DIN2_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
17#[doc = "Field `DIN3_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
18pub type DIN3_MODE_R = crate::FieldReader;
19#[doc = "Field `DIN3_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
20pub type DIN3_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
21#[doc = "Field `DIN4_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"]
22pub type DIN4_MODE_R = crate::FieldReader;
23#[doc = "Field `DIN4_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"]
24pub type DIN4_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
25#[doc = "Field `DIN5_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"]
26pub type DIN5_MODE_R = crate::FieldReader;
27#[doc = "Field `DIN5_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"]
28pub type DIN5_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
29#[doc = "Field `DIN6_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"]
30pub type DIN6_MODE_R = crate::FieldReader;
31#[doc = "Field `DIN6_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"]
32pub type DIN6_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
33#[doc = "Field `DIN7_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"]
34pub type DIN7_MODE_R = crate::FieldReader;
35#[doc = "Field `DIN7_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"]
36pub type DIN7_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
37#[doc = "Field `DINS_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"]
38pub type DINS_MODE_R = crate::FieldReader;
39#[doc = "Field `DINS_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"]
40pub type DINS_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
41impl R {
42 #[doc = "Bits 0:2 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
43 #[inline(always)]
44 pub fn din0_mode(&self) -> DIN0_MODE_R {
45 DIN0_MODE_R::new((self.bits & 7) as u8)
46 }
47 #[doc = "Bits 3:5 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
48 #[inline(always)]
49 pub fn din1_mode(&self) -> DIN1_MODE_R {
50 DIN1_MODE_R::new(((self.bits >> 3) & 7) as u8)
51 }
52 #[doc = "Bits 6:8 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
53 #[inline(always)]
54 pub fn din2_mode(&self) -> DIN2_MODE_R {
55 DIN2_MODE_R::new(((self.bits >> 6) & 7) as u8)
56 }
57 #[doc = "Bits 9:11 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
58 #[inline(always)]
59 pub fn din3_mode(&self) -> DIN3_MODE_R {
60 DIN3_MODE_R::new(((self.bits >> 9) & 7) as u8)
61 }
62 #[doc = "Bits 12:14 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"]
63 #[inline(always)]
64 pub fn din4_mode(&self) -> DIN4_MODE_R {
65 DIN4_MODE_R::new(((self.bits >> 12) & 7) as u8)
66 }
67 #[doc = "Bits 15:17 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"]
68 #[inline(always)]
69 pub fn din5_mode(&self) -> DIN5_MODE_R {
70 DIN5_MODE_R::new(((self.bits >> 15) & 7) as u8)
71 }
72 #[doc = "Bits 18:20 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"]
73 #[inline(always)]
74 pub fn din6_mode(&self) -> DIN6_MODE_R {
75 DIN6_MODE_R::new(((self.bits >> 18) & 7) as u8)
76 }
77 #[doc = "Bits 21:23 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"]
78 #[inline(always)]
79 pub fn din7_mode(&self) -> DIN7_MODE_R {
80 DIN7_MODE_R::new(((self.bits >> 21) & 7) as u8)
81 }
82 #[doc = "Bits 24:26 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"]
83 #[inline(always)]
84 pub fn dins_mode(&self) -> DINS_MODE_R {
85 DINS_MODE_R::new(((self.bits >> 24) & 7) as u8)
86 }
87}
88#[cfg(feature = "impl-register-debug")]
89impl core::fmt::Debug for R {
90 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
91 f.debug_struct("DIN_MODE")
92 .field("din0_mode", &self.din0_mode())
93 .field("din1_mode", &self.din1_mode())
94 .field("din2_mode", &self.din2_mode())
95 .field("din3_mode", &self.din3_mode())
96 .field("din4_mode", &self.din4_mode())
97 .field("din5_mode", &self.din5_mode())
98 .field("din6_mode", &self.din6_mode())
99 .field("din7_mode", &self.din7_mode())
100 .field("dins_mode", &self.dins_mode())
101 .finish()
102 }
103}
104impl W {
105 #[doc = "Bits 0:2 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
106 #[inline(always)]
107 pub fn din0_mode(&mut self) -> DIN0_MODE_W<DIN_MODE_SPEC> {
108 DIN0_MODE_W::new(self, 0)
109 }
110 #[doc = "Bits 3:5 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
111 #[inline(always)]
112 pub fn din1_mode(&mut self) -> DIN1_MODE_W<DIN_MODE_SPEC> {
113 DIN1_MODE_W::new(self, 3)
114 }
115 #[doc = "Bits 6:8 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
116 #[inline(always)]
117 pub fn din2_mode(&mut self) -> DIN2_MODE_W<DIN_MODE_SPEC> {
118 DIN2_MODE_W::new(self, 6)
119 }
120 #[doc = "Bits 9:11 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
121 #[inline(always)]
122 pub fn din3_mode(&mut self) -> DIN3_MODE_W<DIN_MODE_SPEC> {
123 DIN3_MODE_W::new(self, 9)
124 }
125 #[doc = "Bits 12:14 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"]
126 #[inline(always)]
127 pub fn din4_mode(&mut self) -> DIN4_MODE_W<DIN_MODE_SPEC> {
128 DIN4_MODE_W::new(self, 12)
129 }
130 #[doc = "Bits 15:17 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"]
131 #[inline(always)]
132 pub fn din5_mode(&mut self) -> DIN5_MODE_W<DIN_MODE_SPEC> {
133 DIN5_MODE_W::new(self, 15)
134 }
135 #[doc = "Bits 18:20 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"]
136 #[inline(always)]
137 pub fn din6_mode(&mut self) -> DIN6_MODE_W<DIN_MODE_SPEC> {
138 DIN6_MODE_W::new(self, 18)
139 }
140 #[doc = "Bits 21:23 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"]
141 #[inline(always)]
142 pub fn din7_mode(&mut self) -> DIN7_MODE_W<DIN_MODE_SPEC> {
143 DIN7_MODE_W::new(self, 21)
144 }
145 #[doc = "Bits 24:26 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"]
146 #[inline(always)]
147 pub fn dins_mode(&mut self) -> DINS_MODE_W<DIN_MODE_SPEC> {
148 DINS_MODE_W::new(self, 24)
149 }
150}
151#[doc = "MSPI flash input timing delay mode control register\n\nYou can [`read`](crate::Reg::read) this register and get [`din_mode::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`din_mode::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
152pub struct DIN_MODE_SPEC;
153impl crate::RegisterSpec for DIN_MODE_SPEC {
154 type Ux = u32;
155}
156#[doc = "`read()` method returns [`din_mode::R`](R) reader structure"]
157impl crate::Readable for DIN_MODE_SPEC {}
158#[doc = "`write(|w| ..)` method takes [`din_mode::W`](W) writer structure"]
159impl crate::Writable for DIN_MODE_SPEC {
160 type Safety = crate::Unsafe;
161 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
162 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
163}
164#[doc = "`reset()` method sets DIN_MODE to value 0"]
165impl crate::Resettable for DIN_MODE_SPEC {
166 const RESET_VALUE: u32 = 0;
167}