1#[doc = "Register `CTRL2` reader"]
2pub type R = crate::R<CTRL2_SPEC>;
3#[doc = "Register `CTRL2` writer"]
4pub type W = crate::W<CTRL2_SPEC>;
5#[doc = "Field `CS_SETUP_TIME` reader - (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit."]
6pub type CS_SETUP_TIME_R = crate::FieldReader;
7#[doc = "Field `CS_SETUP_TIME` writer - (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit."]
8pub type CS_SETUP_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9#[doc = "Field `CS_HOLD_TIME` reader - SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit."]
10pub type CS_HOLD_TIME_R = crate::FieldReader;
11#[doc = "Field `CS_HOLD_TIME` writer - SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit."]
12pub type CS_HOLD_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
13#[doc = "Field `ECC_CS_HOLD_TIME` reader - SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash."]
14pub type ECC_CS_HOLD_TIME_R = crate::FieldReader;
15#[doc = "Field `ECC_SKIP_PAGE_CORNER` reader - 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash."]
16pub type ECC_SKIP_PAGE_CORNER_R = crate::BitReader;
17#[doc = "Field `ECC_16TO18_BYTE_EN` reader - Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash."]
18pub type ECC_16TO18_BYTE_EN_R = crate::BitReader;
19#[doc = "Field `SPLIT_TRANS_EN` reader - Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not."]
20pub type SPLIT_TRANS_EN_R = crate::BitReader;
21#[doc = "Field `CS_HOLD_DELAY` reader - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY\\[5:0\\] + 1) MSPI core clock cycles."]
22pub type CS_HOLD_DELAY_R = crate::FieldReader;
23#[doc = "Field `CS_HOLD_DELAY` writer - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY\\[5:0\\] + 1) MSPI core clock cycles."]
24pub type CS_HOLD_DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
25#[doc = "Field `SYNC_RESET` writer - The spi0_mst_st and spi0_slv_st will be reset."]
26pub type SYNC_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
27impl R {
28 #[doc = "Bits 0:4 - (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit."]
29 #[inline(always)]
30 pub fn cs_setup_time(&self) -> CS_SETUP_TIME_R {
31 CS_SETUP_TIME_R::new((self.bits & 0x1f) as u8)
32 }
33 #[doc = "Bits 5:9 - SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit."]
34 #[inline(always)]
35 pub fn cs_hold_time(&self) -> CS_HOLD_TIME_R {
36 CS_HOLD_TIME_R::new(((self.bits >> 5) & 0x1f) as u8)
37 }
38 #[doc = "Bits 10:12 - SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash."]
39 #[inline(always)]
40 pub fn ecc_cs_hold_time(&self) -> ECC_CS_HOLD_TIME_R {
41 ECC_CS_HOLD_TIME_R::new(((self.bits >> 10) & 7) as u8)
42 }
43 #[doc = "Bit 13 - 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash."]
44 #[inline(always)]
45 pub fn ecc_skip_page_corner(&self) -> ECC_SKIP_PAGE_CORNER_R {
46 ECC_SKIP_PAGE_CORNER_R::new(((self.bits >> 13) & 1) != 0)
47 }
48 #[doc = "Bit 14 - Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash."]
49 #[inline(always)]
50 pub fn ecc_16to18_byte_en(&self) -> ECC_16TO18_BYTE_EN_R {
51 ECC_16TO18_BYTE_EN_R::new(((self.bits >> 14) & 1) != 0)
52 }
53 #[doc = "Bit 24 - Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not."]
54 #[inline(always)]
55 pub fn split_trans_en(&self) -> SPLIT_TRANS_EN_R {
56 SPLIT_TRANS_EN_R::new(((self.bits >> 24) & 1) != 0)
57 }
58 #[doc = "Bits 25:30 - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY\\[5:0\\] + 1) MSPI core clock cycles."]
59 #[inline(always)]
60 pub fn cs_hold_delay(&self) -> CS_HOLD_DELAY_R {
61 CS_HOLD_DELAY_R::new(((self.bits >> 25) & 0x3f) as u8)
62 }
63}
64#[cfg(feature = "impl-register-debug")]
65impl core::fmt::Debug for R {
66 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
67 f.debug_struct("CTRL2")
68 .field("cs_setup_time", &self.cs_setup_time())
69 .field("cs_hold_time", &self.cs_hold_time())
70 .field("ecc_cs_hold_time", &self.ecc_cs_hold_time())
71 .field("ecc_skip_page_corner", &self.ecc_skip_page_corner())
72 .field("ecc_16to18_byte_en", &self.ecc_16to18_byte_en())
73 .field("split_trans_en", &self.split_trans_en())
74 .field("cs_hold_delay", &self.cs_hold_delay())
75 .finish()
76 }
77}
78impl W {
79 #[doc = "Bits 0:4 - (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit."]
80 #[inline(always)]
81 pub fn cs_setup_time(&mut self) -> CS_SETUP_TIME_W<CTRL2_SPEC> {
82 CS_SETUP_TIME_W::new(self, 0)
83 }
84 #[doc = "Bits 5:9 - SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit."]
85 #[inline(always)]
86 pub fn cs_hold_time(&mut self) -> CS_HOLD_TIME_W<CTRL2_SPEC> {
87 CS_HOLD_TIME_W::new(self, 5)
88 }
89 #[doc = "Bits 25:30 - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY\\[5:0\\] + 1) MSPI core clock cycles."]
90 #[inline(always)]
91 pub fn cs_hold_delay(&mut self) -> CS_HOLD_DELAY_W<CTRL2_SPEC> {
92 CS_HOLD_DELAY_W::new(self, 25)
93 }
94 #[doc = "Bit 31 - The spi0_mst_st and spi0_slv_st will be reset."]
95 #[inline(always)]
96 pub fn sync_reset(&mut self) -> SYNC_RESET_W<CTRL2_SPEC> {
97 SYNC_RESET_W::new(self, 31)
98 }
99}
100#[doc = "SPI0 control2 register.\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
101pub struct CTRL2_SPEC;
102impl crate::RegisterSpec for CTRL2_SPEC {
103 type Ux = u32;
104}
105#[doc = "`read()` method returns [`ctrl2::R`](R) reader structure"]
106impl crate::Readable for CTRL2_SPEC {}
107#[doc = "`write(|w| ..)` method takes [`ctrl2::W`](W) writer structure"]
108impl crate::Writable for CTRL2_SPEC {
109 type Safety = crate::Unsafe;
110 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
111 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
112}
113#[doc = "`reset()` method sets CTRL2 to value 0x2c21"]
114impl crate::Resettable for CTRL2_SPEC {
115 const RESET_VALUE: u32 = 0x2c21;
116}