esp32h2/i2c0/
filter_cfg.rs

1#[doc = "Register `FILTER_CFG` reader"]
2pub type R = crate::R<FILTER_CFG_SPEC>;
3#[doc = "Register `FILTER_CFG` writer"]
4pub type W = crate::W<FILTER_CFG_SPEC>;
5#[doc = "Field `SCL_FILTER_THRES` reader - When a pulse on the SCL input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse."]
6pub type SCL_FILTER_THRES_R = crate::FieldReader;
7#[doc = "Field `SCL_FILTER_THRES` writer - When a pulse on the SCL input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse."]
8pub type SCL_FILTER_THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `SDA_FILTER_THRES` reader - When a pulse on the SDA input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse."]
10pub type SDA_FILTER_THRES_R = crate::FieldReader;
11#[doc = "Field `SDA_FILTER_THRES` writer - When a pulse on the SDA input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse."]
12pub type SDA_FILTER_THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13#[doc = "Field `SCL_FILTER_EN` reader - This is the filter enable bit for SCL."]
14pub type SCL_FILTER_EN_R = crate::BitReader;
15#[doc = "Field `SCL_FILTER_EN` writer - This is the filter enable bit for SCL."]
16pub type SCL_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SDA_FILTER_EN` reader - This is the filter enable bit for SDA."]
18pub type SDA_FILTER_EN_R = crate::BitReader;
19#[doc = "Field `SDA_FILTER_EN` writer - This is the filter enable bit for SDA."]
20pub type SDA_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bits 0:3 - When a pulse on the SCL input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse."]
23    #[inline(always)]
24    pub fn scl_filter_thres(&self) -> SCL_FILTER_THRES_R {
25        SCL_FILTER_THRES_R::new((self.bits & 0x0f) as u8)
26    }
27    #[doc = "Bits 4:7 - When a pulse on the SDA input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse."]
28    #[inline(always)]
29    pub fn sda_filter_thres(&self) -> SDA_FILTER_THRES_R {
30        SDA_FILTER_THRES_R::new(((self.bits >> 4) & 0x0f) as u8)
31    }
32    #[doc = "Bit 8 - This is the filter enable bit for SCL."]
33    #[inline(always)]
34    pub fn scl_filter_en(&self) -> SCL_FILTER_EN_R {
35        SCL_FILTER_EN_R::new(((self.bits >> 8) & 1) != 0)
36    }
37    #[doc = "Bit 9 - This is the filter enable bit for SDA."]
38    #[inline(always)]
39    pub fn sda_filter_en(&self) -> SDA_FILTER_EN_R {
40        SDA_FILTER_EN_R::new(((self.bits >> 9) & 1) != 0)
41    }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("FILTER_CFG")
47            .field("scl_filter_thres", &self.scl_filter_thres())
48            .field("sda_filter_thres", &self.sda_filter_thres())
49            .field("scl_filter_en", &self.scl_filter_en())
50            .field("sda_filter_en", &self.sda_filter_en())
51            .finish()
52    }
53}
54impl W {
55    #[doc = "Bits 0:3 - When a pulse on the SCL input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse."]
56    #[inline(always)]
57    pub fn scl_filter_thres(&mut self) -> SCL_FILTER_THRES_W<FILTER_CFG_SPEC> {
58        SCL_FILTER_THRES_W::new(self, 0)
59    }
60    #[doc = "Bits 4:7 - When a pulse on the SDA input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse."]
61    #[inline(always)]
62    pub fn sda_filter_thres(&mut self) -> SDA_FILTER_THRES_W<FILTER_CFG_SPEC> {
63        SDA_FILTER_THRES_W::new(self, 4)
64    }
65    #[doc = "Bit 8 - This is the filter enable bit for SCL."]
66    #[inline(always)]
67    pub fn scl_filter_en(&mut self) -> SCL_FILTER_EN_W<FILTER_CFG_SPEC> {
68        SCL_FILTER_EN_W::new(self, 8)
69    }
70    #[doc = "Bit 9 - This is the filter enable bit for SDA."]
71    #[inline(always)]
72    pub fn sda_filter_en(&mut self) -> SDA_FILTER_EN_W<FILTER_CFG_SPEC> {
73        SDA_FILTER_EN_W::new(self, 9)
74    }
75}
76#[doc = "SCL and SDA filter configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`filter_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`filter_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
77pub struct FILTER_CFG_SPEC;
78impl crate::RegisterSpec for FILTER_CFG_SPEC {
79    type Ux = u32;
80}
81#[doc = "`read()` method returns [`filter_cfg::R`](R) reader structure"]
82impl crate::Readable for FILTER_CFG_SPEC {}
83#[doc = "`write(|w| ..)` method takes [`filter_cfg::W`](W) writer structure"]
84impl crate::Writable for FILTER_CFG_SPEC {
85    type Safety = crate::Unsafe;
86    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
87    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
88}
89#[doc = "`reset()` method sets FILTER_CFG to value 0x0300"]
90impl crate::Resettable for FILTER_CFG_SPEC {
91    const RESET_VALUE: u32 = 0x0300;
92}
esp32h2/i2c0/filter_cfg.rs

esp32h2/i2c0/
filter_cfg.rs
