esp32h2/dma/out_int_ch/
raw.rs

1#[doc = "Register `RAW` reader"]
2pub type R = crate::R<RAW_SPEC>;
3#[doc = "Register `RAW` writer"]
4pub type W = crate::W<RAW_SPEC>;
5#[doc = "Field `OUT_DONE` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."]
6pub type OUT_DONE_R = crate::BitReader;
7#[doc = "Field `OUT_DONE` writer - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."]
8pub type OUT_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `OUT_EOF` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."]
10pub type OUT_EOF_R = crate::BitReader;
11#[doc = "Field `OUT_EOF` writer - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."]
12pub type OUT_EOF_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `OUT_DSCR_ERR` reader - The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error and the second and third word error of outlink descriptor for Tx channel 0."]
14pub type OUT_DSCR_ERR_R = crate::BitReader;
15#[doc = "Field `OUT_DSCR_ERR` writer - The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error and the second and third word error of outlink descriptor for Tx channel 0."]
16pub type OUT_DSCR_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `OUT_TOTAL_EOF` reader - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."]
18pub type OUT_TOTAL_EOF_R = crate::BitReader;
19#[doc = "Field `OUT_TOTAL_EOF` writer - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."]
20pub type OUT_TOTAL_EOF_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `OUTFIFO_OVF` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow."]
22pub type OUTFIFO_OVF_R = crate::BitReader;
23#[doc = "Field `OUTFIFO_OVF` writer - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow."]
24pub type OUTFIFO_OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `OUTFIFO_UDF` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow."]
26pub type OUTFIFO_UDF_R = crate::BitReader;
27#[doc = "Field `OUTFIFO_UDF` writer - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow."]
28pub type OUTFIFO_UDF_W<'a, REG> = crate::BitWriter<'a, REG>;
29impl R {
30    #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."]
31    #[inline(always)]
32    pub fn out_done(&self) -> OUT_DONE_R {
33        OUT_DONE_R::new((self.bits & 1) != 0)
34    }
35    #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."]
36    #[inline(always)]
37    pub fn out_eof(&self) -> OUT_EOF_R {
38        OUT_EOF_R::new(((self.bits >> 1) & 1) != 0)
39    }
40    #[doc = "Bit 2 - The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error and the second and third word error of outlink descriptor for Tx channel 0."]
41    #[inline(always)]
42    pub fn out_dscr_err(&self) -> OUT_DSCR_ERR_R {
43        OUT_DSCR_ERR_R::new(((self.bits >> 2) & 1) != 0)
44    }
45    #[doc = "Bit 3 - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."]
46    #[inline(always)]
47    pub fn out_total_eof(&self) -> OUT_TOTAL_EOF_R {
48        OUT_TOTAL_EOF_R::new(((self.bits >> 3) & 1) != 0)
49    }
50    #[doc = "Bit 4 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow."]
51    #[inline(always)]
52    pub fn outfifo_ovf(&self) -> OUTFIFO_OVF_R {
53        OUTFIFO_OVF_R::new(((self.bits >> 4) & 1) != 0)
54    }
55    #[doc = "Bit 5 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow."]
56    #[inline(always)]
57    pub fn outfifo_udf(&self) -> OUTFIFO_UDF_R {
58        OUTFIFO_UDF_R::new(((self.bits >> 5) & 1) != 0)
59    }
60}
61#[cfg(feature = "impl-register-debug")]
62impl core::fmt::Debug for R {
63    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
64        f.debug_struct("RAW")
65            .field("out_done", &self.out_done())
66            .field("out_eof", &self.out_eof())
67            .field("out_dscr_err", &self.out_dscr_err())
68            .field("out_total_eof", &self.out_total_eof())
69            .field("outfifo_ovf", &self.outfifo_ovf())
70            .field("outfifo_udf", &self.outfifo_udf())
71            .finish()
72    }
73}
74impl W {
75    #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."]
76    #[inline(always)]
77    pub fn out_done(&mut self) -> OUT_DONE_W<RAW_SPEC> {
78        OUT_DONE_W::new(self, 0)
79    }
80    #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."]
81    #[inline(always)]
82    pub fn out_eof(&mut self) -> OUT_EOF_W<RAW_SPEC> {
83        OUT_EOF_W::new(self, 1)
84    }
85    #[doc = "Bit 2 - The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error and the second and third word error of outlink descriptor for Tx channel 0."]
86    #[inline(always)]
87    pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W<RAW_SPEC> {
88        OUT_DSCR_ERR_W::new(self, 2)
89    }
90    #[doc = "Bit 3 - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."]
91    #[inline(always)]
92    pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<RAW_SPEC> {
93        OUT_TOTAL_EOF_W::new(self, 3)
94    }
95    #[doc = "Bit 4 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow."]
96    #[inline(always)]
97    pub fn outfifo_ovf(&mut self) -> OUTFIFO_OVF_W<RAW_SPEC> {
98        OUTFIFO_OVF_W::new(self, 4)
99    }
100    #[doc = "Bit 5 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow."]
101    #[inline(always)]
102    pub fn outfifo_udf(&mut self) -> OUTFIFO_UDF_W<RAW_SPEC> {
103        OUTFIFO_UDF_W::new(self, 5)
104    }
105}
106#[doc = "Raw status interrupt of channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
107pub struct RAW_SPEC;
108impl crate::RegisterSpec for RAW_SPEC {
109    type Ux = u32;
110}
111#[doc = "`read()` method returns [`raw::R`](R) reader structure"]
112impl crate::Readable for RAW_SPEC {}
113#[doc = "`write(|w| ..)` method takes [`raw::W`](W) writer structure"]
114impl crate::Writable for RAW_SPEC {
115    type Safety = crate::Unsafe;
116    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
117    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
118}
119#[doc = "`reset()` method sets RAW to value 0"]
120impl crate::Resettable for RAW_SPEC {
121    const RESET_VALUE: u32 = 0;
122}
esp32h2/dma/out_int_ch/raw.rs

esp32h2/dma/out_int_ch/
raw.rs
