Expand description
SPI0 external RAM mode control register
Structs§
- SRAM_
CMD_ SPEC - SPI0 external RAM mode control register
Type Aliases§
- R
- Register
SRAM_CMD
reader - SADDR_
DUAL_ R - Field
SADDR_DUAL
reader - For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio. - SADDR_
OCT_ R - Field
SADDR_OCT
reader - For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. - SADDR_
QUAD_ R - Field
SADDR_QUAD
reader - For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. - SCLK_
MODE_ R - Field
SCLK_MODE
reader - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on. - SCMD_
OCT_ R - Field
SCMD_OCT
reader - For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. - SCMD_
QUAD_ R - Field
SCMD_QUAD
reader - For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. - SDIN_
DUAL_ R - Field
SDIN_DUAL
reader - For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio. - SDIN_
OCT_ R - Field
SDIN_OCT
reader - For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. - SDIN_
QUAD_ R - Field
SDIN_QUAD
reader - For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. - SDOUT_
DUAL_ R - Field
SDOUT_DUAL
reader - For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio. - SDOUT_
OCT_ R - Field
SDOUT_OCT
reader - For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. - SDOUT_
QUAD_ R - Field
SDOUT_QUAD
reader - For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. - SDUMMY_
RIN_ R - Field
SDUMMY_RIN
reader - In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller. - SDUMMY_
RIN_ W - Field
SDUMMY_RIN
writer - In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller. - SDUMMY_
WOUT_ R - Field
SDUMMY_WOUT
reader - In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller. - SPI_
SMEM_ DATA_ IE_ ALWAYS_ ON_ R - Field
SPI_SMEM_DATA_IE_ALWAYS_ON
reader - When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others. - SPI_
SMEM_ DQS_ IE_ ALWAYS_ ON_ R - Field
SPI_SMEM_DQS_IE_ALWAYS_ON
reader - When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others. - SPI_
SMEM_ WDUMMY_ ALWAYS_ OUT_ R - Field
SPI_SMEM_WDUMMY_ALWAYS_OUT
reader - In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO[7:0] is output by the MSPI controller. - SPI_
SMEM_ WDUMMY_ DQS_ ALWAYS_ OUT_ R - Field
SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT
reader - In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller. - SWB_
MODE_ R - Field
SWB_MODE
reader - Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd_mode bit. - W
- Register
SRAM_CMD
writer