Expand description
Parallel TX general configuration register.
Structs§
- TX_
GENRL_ CFG_ SPEC - Parallel TX general configuration register.
Type Aliases§
- R
- Register
TX_GENRL_CFG
reader - TX_
GATING_ EN_ R - Field
TX_GATING_EN
reader - Set this bit to enable the clock gating of output tx clock. - TX_
GATING_ EN_ W - Field
TX_GATING_EN
writer - Set this bit to enable the clock gating of output tx clock. - TX_
IDLE_ VALUE_ R - Field
TX_IDLE_VALUE
reader - Configures bus value of transmitter in IDLE state. - TX_
IDLE_ VALUE_ W - Field
TX_IDLE_VALUE
writer - Configures bus value of transmitter in IDLE state. - TX_
VALID_ OUTPUT_ EN_ R - Field
TX_VALID_OUTPUT_EN
reader - Set this bit to enable the output of tx data valid signal. - TX_
VALID_ OUTPUT_ EN_ W - Field
TX_VALID_OUTPUT_EN
writer - Set this bit to enable the output of tx data valid signal. - W
- Register
TX_GENRL_CFG
writer