Expand description
RISC-V Trace Encoder
Modules
- Clock gate control register
- Version control register
- fifo status register
- interrupt clear register
- interrupt enable register
- interrupt status register
- mem addr update
- mem current addr
- mem end addr
- mem start addr
- resync configuration register
- trigger register
Structs
- Register block
Type Aliases
- CLOCK_GATE (rw) register accessor: Clock gate control register
- DATE (rw) register accessor: Version control register
- FIFO_STATUS (r) register accessor: fifo status register
- INTR_CLR (w) register accessor: interrupt clear register
- INTR_ENA (rw) register accessor: interrupt enable register
- INTR_RAW (r) register accessor: interrupt status register
- MEM_ADDR_UPDATE (w) register accessor: mem addr update
- MEM_CURRENT_ADDR (r) register accessor: mem current addr
- MEM_END_ADDR (rw) register accessor: mem end addr
- MEM_START_ADDR (rw) register accessor: mem start addr
- RESYNC_PROLONGED (rw) register accessor: resync configuration register
- TRIGGER (rw) register accessor: trigger register