Module esp32h2::spi0::spi_mem_ctrl2
source · Expand description
SPI0 control2 register.
Structs
- SPI0 control2 register.
Type Aliases
- Register
SPI_MEM_CTRL2
reader - Field
SPI_MEM_CS_HOLD_DELAY
reader - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. - Field
SPI_MEM_CS_HOLD_DELAY
writer - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. - Field
SPI_MEM_CS_HOLD_TIME
reader - SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit. - Field
SPI_MEM_CS_HOLD_TIME
writer - SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit. - Field
SPI_MEM_CS_SETUP_TIME
reader - (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit. - Field
SPI_MEM_CS_SETUP_TIME
writer - (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit. - Field
SPI_MEM_ECC_16TO18_BYTE_EN
reader - Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash. - Field
SPI_MEM_ECC_CS_HOLD_TIME
reader - SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash. - Field
SPI_MEM_ECC_SKIP_PAGE_CORNER
reader - 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash. - Field
SPI_MEM_SPLIT_TRANS_EN
reader - Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not. - Field
SPI_MEM_SYNC_RESET
writer - The spi0_mst_st and spi0_slv_st will be reset. - Register
SPI_MEM_CTRL2
writer