Module esp32h2::spi0::spi_mem_cache_fctrl

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Expand description

SPI0 bit mode control register.

Structs

Type Aliases

  • R
    Register SPI_MEM_CACHE_FCTRL reader
  • SPI_CLOSE_AXI_INF_EN_R
    Field SPI_CLOSE_AXI_INF_EN reader - Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP.
  • SPI_CLOSE_AXI_INF_EN_W
    Field SPI_CLOSE_AXI_INF_EN writer - Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP.
  • SPI_MEM_AXI_REQ_EN_R
    Field SPI_MEM_AXI_REQ_EN reader - For SPI0, AXI master access enable, 1: enable, 0:disable.
  • SPI_MEM_AXI_REQ_EN_W
    Field SPI_MEM_AXI_REQ_EN writer - For SPI0, AXI master access enable, 1: enable, 0:disable.
  • SPI_MEM_CACHE_FLASH_USR_CMD_R
    Field SPI_MEM_CACHE_FLASH_USR_CMD reader - For SPI0, cache read flash for user define command, 1: enable, 0:disable.
  • SPI_MEM_CACHE_FLASH_USR_CMD_W
    Field SPI_MEM_CACHE_FLASH_USR_CMD writer - For SPI0, cache read flash for user define command, 1: enable, 0:disable.
  • SPI_MEM_CACHE_USR_ADDR_4BYTE_R
    Field SPI_MEM_CACHE_USR_ADDR_4BYTE reader - For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable.
  • SPI_MEM_CACHE_USR_ADDR_4BYTE_W
    Field SPI_MEM_CACHE_USR_ADDR_4BYTE writer - For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable.
  • SPI_MEM_FADDR_DUAL_R
    Field SPI_MEM_FADDR_DUAL reader - For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
  • SPI_MEM_FADDR_DUAL_W
    Field SPI_MEM_FADDR_DUAL writer - For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
  • SPI_MEM_FADDR_QUAD_R
    Field SPI_MEM_FADDR_QUAD reader - For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
  • SPI_MEM_FADDR_QUAD_W
    Field SPI_MEM_FADDR_QUAD writer - For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
  • SPI_MEM_FDIN_DUAL_R
    Field SPI_MEM_FDIN_DUAL reader - For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
  • SPI_MEM_FDIN_DUAL_W
    Field SPI_MEM_FDIN_DUAL writer - For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
  • SPI_MEM_FDIN_QUAD_R
    Field SPI_MEM_FDIN_QUAD reader - For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
  • SPI_MEM_FDIN_QUAD_W
    Field SPI_MEM_FDIN_QUAD writer - For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
  • SPI_MEM_FDOUT_DUAL_R
    Field SPI_MEM_FDOUT_DUAL reader - For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
  • SPI_MEM_FDOUT_DUAL_W
    Field SPI_MEM_FDOUT_DUAL writer - For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
  • SPI_MEM_FDOUT_QUAD_R
    Field SPI_MEM_FDOUT_QUAD reader - For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
  • SPI_MEM_FDOUT_QUAD_W
    Field SPI_MEM_FDOUT_QUAD writer - For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
  • SPI_SAME_AW_AR_ADDR_CHK_EN_R
    Field SPI_SAME_AW_AR_ADDR_CHK_EN reader - Set this bit to check AXI read/write the same address region.
  • W
    Register SPI_MEM_CACHE_FCTRL writer