1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CTRL_SPEC>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CTRL_SPEC>;
5#[doc = "Field `FDUMMY_RIN` reader - In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."]
6pub type FDUMMY_RIN_R = crate::BitReader;
7#[doc = "Field `FDUMMY_RIN` writer - In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."]
8pub type FDUMMY_RIN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `FDUMMY_WOUT` reader - In the dummy phase of a MSPI write data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."]
10pub type FDUMMY_WOUT_R = crate::BitReader;
11#[doc = "Field `FDUMMY_WOUT` writer - In the dummy phase of a MSPI write data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."]
12pub type FDUMMY_WOUT_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `FDOUT_OCT` reader - Apply 8 signals during write-data phase 1:enable 0: disable"]
14pub type FDOUT_OCT_R = crate::BitReader;
15#[doc = "Field `FDIN_OCT` reader - Apply 8 signals during read-data phase 1:enable 0: disable"]
16pub type FDIN_OCT_R = crate::BitReader;
17#[doc = "Field `FADDR_OCT` reader - Apply 8 signals during address phase 1:enable 0: disable"]
18pub type FADDR_OCT_R = crate::BitReader;
19#[doc = "Field `FCMD_QUAD` reader - Apply 4 signals during command phase 1:enable 0: disable"]
20pub type FCMD_QUAD_R = crate::BitReader;
21#[doc = "Field `FCMD_QUAD` writer - Apply 4 signals during command phase 1:enable 0: disable"]
22pub type FCMD_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
23#[doc = "Field `FCMD_OCT` reader - Apply 8 signals during command phase 1:enable 0: disable"]
24pub type FCMD_OCT_R = crate::BitReader;
25#[doc = "Field `FCS_CRC_EN` reader - For SPI1, initialize crc32 module before writing encrypted data to flash. Active low."]
26pub type FCS_CRC_EN_R = crate::BitReader;
27#[doc = "Field `TX_CRC_EN` reader - For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable"]
28pub type TX_CRC_EN_R = crate::BitReader;
29#[doc = "Field `FASTRD_MODE` reader - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable."]
30pub type FASTRD_MODE_R = crate::BitReader;
31#[doc = "Field `FASTRD_MODE` writer - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable."]
32pub type FASTRD_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `FREAD_DUAL` reader - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable."]
34pub type FREAD_DUAL_R = crate::BitReader;
35#[doc = "Field `FREAD_DUAL` writer - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable."]
36pub type FREAD_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `RESANDRES` reader - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable."]
38pub type RESANDRES_R = crate::BitReader;
39#[doc = "Field `RESANDRES` writer - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable."]
40pub type RESANDRES_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `Q_POL` reader - The bit is used to set MISO line polarity, 1: high 0, low"]
42pub type Q_POL_R = crate::BitReader;
43#[doc = "Field `Q_POL` writer - The bit is used to set MISO line polarity, 1: high 0, low"]
44pub type Q_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `D_POL` reader - The bit is used to set MOSI line polarity, 1: high 0, low"]
46pub type D_POL_R = crate::BitReader;
47#[doc = "Field `D_POL` writer - The bit is used to set MOSI line polarity, 1: high 0, low"]
48pub type D_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `FREAD_QUAD` reader - In the read operations read-data phase apply 4 signals. 1: enable 0: disable."]
50pub type FREAD_QUAD_R = crate::BitReader;
51#[doc = "Field `FREAD_QUAD` writer - In the read operations read-data phase apply 4 signals. 1: enable 0: disable."]
52pub type FREAD_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `WP` reader - Write protect signal output when SPI is idle. 1: output high, 0: output low."]
54pub type WP_R = crate::BitReader;
55#[doc = "Field `WP` writer - Write protect signal output when SPI is idle. 1: output high, 0: output low."]
56pub type WP_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `WRSR_2B` reader - two bytes data will be written to status register when it is set. 1: enable 0: disable."]
58pub type WRSR_2B_R = crate::BitReader;
59#[doc = "Field `WRSR_2B` writer - two bytes data will be written to status register when it is set. 1: enable 0: disable."]
60pub type WRSR_2B_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `FREAD_DIO` reader - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable."]
62pub type FREAD_DIO_R = crate::BitReader;
63#[doc = "Field `FREAD_DIO` writer - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable."]
64pub type FREAD_DIO_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `FREAD_QIO` reader - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable."]
66pub type FREAD_QIO_R = crate::BitReader;
67#[doc = "Field `FREAD_QIO` writer - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable."]
68pub type FREAD_QIO_W<'a, REG> = crate::BitWriter<'a, REG>;
69impl R {
70 #[doc = "Bit 2 - In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."]
71 #[inline(always)]
72 pub fn fdummy_rin(&self) -> FDUMMY_RIN_R {
73 FDUMMY_RIN_R::new(((self.bits >> 2) & 1) != 0)
74 }
75 #[doc = "Bit 3 - In the dummy phase of a MSPI write data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."]
76 #[inline(always)]
77 pub fn fdummy_wout(&self) -> FDUMMY_WOUT_R {
78 FDUMMY_WOUT_R::new(((self.bits >> 3) & 1) != 0)
79 }
80 #[doc = "Bit 4 - Apply 8 signals during write-data phase 1:enable 0: disable"]
81 #[inline(always)]
82 pub fn fdout_oct(&self) -> FDOUT_OCT_R {
83 FDOUT_OCT_R::new(((self.bits >> 4) & 1) != 0)
84 }
85 #[doc = "Bit 5 - Apply 8 signals during read-data phase 1:enable 0: disable"]
86 #[inline(always)]
87 pub fn fdin_oct(&self) -> FDIN_OCT_R {
88 FDIN_OCT_R::new(((self.bits >> 5) & 1) != 0)
89 }
90 #[doc = "Bit 6 - Apply 8 signals during address phase 1:enable 0: disable"]
91 #[inline(always)]
92 pub fn faddr_oct(&self) -> FADDR_OCT_R {
93 FADDR_OCT_R::new(((self.bits >> 6) & 1) != 0)
94 }
95 #[doc = "Bit 8 - Apply 4 signals during command phase 1:enable 0: disable"]
96 #[inline(always)]
97 pub fn fcmd_quad(&self) -> FCMD_QUAD_R {
98 FCMD_QUAD_R::new(((self.bits >> 8) & 1) != 0)
99 }
100 #[doc = "Bit 9 - Apply 8 signals during command phase 1:enable 0: disable"]
101 #[inline(always)]
102 pub fn fcmd_oct(&self) -> FCMD_OCT_R {
103 FCMD_OCT_R::new(((self.bits >> 9) & 1) != 0)
104 }
105 #[doc = "Bit 10 - For SPI1, initialize crc32 module before writing encrypted data to flash. Active low."]
106 #[inline(always)]
107 pub fn fcs_crc_en(&self) -> FCS_CRC_EN_R {
108 FCS_CRC_EN_R::new(((self.bits >> 10) & 1) != 0)
109 }
110 #[doc = "Bit 11 - For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable"]
111 #[inline(always)]
112 pub fn tx_crc_en(&self) -> TX_CRC_EN_R {
113 TX_CRC_EN_R::new(((self.bits >> 11) & 1) != 0)
114 }
115 #[doc = "Bit 13 - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable."]
116 #[inline(always)]
117 pub fn fastrd_mode(&self) -> FASTRD_MODE_R {
118 FASTRD_MODE_R::new(((self.bits >> 13) & 1) != 0)
119 }
120 #[doc = "Bit 14 - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable."]
121 #[inline(always)]
122 pub fn fread_dual(&self) -> FREAD_DUAL_R {
123 FREAD_DUAL_R::new(((self.bits >> 14) & 1) != 0)
124 }
125 #[doc = "Bit 15 - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable."]
126 #[inline(always)]
127 pub fn resandres(&self) -> RESANDRES_R {
128 RESANDRES_R::new(((self.bits >> 15) & 1) != 0)
129 }
130 #[doc = "Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low"]
131 #[inline(always)]
132 pub fn q_pol(&self) -> Q_POL_R {
133 Q_POL_R::new(((self.bits >> 18) & 1) != 0)
134 }
135 #[doc = "Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low"]
136 #[inline(always)]
137 pub fn d_pol(&self) -> D_POL_R {
138 D_POL_R::new(((self.bits >> 19) & 1) != 0)
139 }
140 #[doc = "Bit 20 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable."]
141 #[inline(always)]
142 pub fn fread_quad(&self) -> FREAD_QUAD_R {
143 FREAD_QUAD_R::new(((self.bits >> 20) & 1) != 0)
144 }
145 #[doc = "Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low."]
146 #[inline(always)]
147 pub fn wp(&self) -> WP_R {
148 WP_R::new(((self.bits >> 21) & 1) != 0)
149 }
150 #[doc = "Bit 22 - two bytes data will be written to status register when it is set. 1: enable 0: disable."]
151 #[inline(always)]
152 pub fn wrsr_2b(&self) -> WRSR_2B_R {
153 WRSR_2B_R::new(((self.bits >> 22) & 1) != 0)
154 }
155 #[doc = "Bit 23 - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable."]
156 #[inline(always)]
157 pub fn fread_dio(&self) -> FREAD_DIO_R {
158 FREAD_DIO_R::new(((self.bits >> 23) & 1) != 0)
159 }
160 #[doc = "Bit 24 - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable."]
161 #[inline(always)]
162 pub fn fread_qio(&self) -> FREAD_QIO_R {
163 FREAD_QIO_R::new(((self.bits >> 24) & 1) != 0)
164 }
165}
166#[cfg(feature = "impl-register-debug")]
167impl core::fmt::Debug for R {
168 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
169 f.debug_struct("CTRL")
170 .field("fdummy_rin", &self.fdummy_rin())
171 .field("fdummy_wout", &self.fdummy_wout())
172 .field("fdout_oct", &self.fdout_oct())
173 .field("fdin_oct", &self.fdin_oct())
174 .field("faddr_oct", &self.faddr_oct())
175 .field("fcmd_quad", &self.fcmd_quad())
176 .field("fcmd_oct", &self.fcmd_oct())
177 .field("fcs_crc_en", &self.fcs_crc_en())
178 .field("tx_crc_en", &self.tx_crc_en())
179 .field("fastrd_mode", &self.fastrd_mode())
180 .field("fread_dual", &self.fread_dual())
181 .field("resandres", &self.resandres())
182 .field("q_pol", &self.q_pol())
183 .field("d_pol", &self.d_pol())
184 .field("fread_quad", &self.fread_quad())
185 .field("wp", &self.wp())
186 .field("wrsr_2b", &self.wrsr_2b())
187 .field("fread_dio", &self.fread_dio())
188 .field("fread_qio", &self.fread_qio())
189 .finish()
190 }
191}
192impl W {
193 #[doc = "Bit 2 - In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."]
194 #[inline(always)]
195 pub fn fdummy_rin(&mut self) -> FDUMMY_RIN_W<CTRL_SPEC> {
196 FDUMMY_RIN_W::new(self, 2)
197 }
198 #[doc = "Bit 3 - In the dummy phase of a MSPI write data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."]
199 #[inline(always)]
200 pub fn fdummy_wout(&mut self) -> FDUMMY_WOUT_W<CTRL_SPEC> {
201 FDUMMY_WOUT_W::new(self, 3)
202 }
203 #[doc = "Bit 8 - Apply 4 signals during command phase 1:enable 0: disable"]
204 #[inline(always)]
205 pub fn fcmd_quad(&mut self) -> FCMD_QUAD_W<CTRL_SPEC> {
206 FCMD_QUAD_W::new(self, 8)
207 }
208 #[doc = "Bit 13 - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable."]
209 #[inline(always)]
210 pub fn fastrd_mode(&mut self) -> FASTRD_MODE_W<CTRL_SPEC> {
211 FASTRD_MODE_W::new(self, 13)
212 }
213 #[doc = "Bit 14 - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable."]
214 #[inline(always)]
215 pub fn fread_dual(&mut self) -> FREAD_DUAL_W<CTRL_SPEC> {
216 FREAD_DUAL_W::new(self, 14)
217 }
218 #[doc = "Bit 15 - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable."]
219 #[inline(always)]
220 pub fn resandres(&mut self) -> RESANDRES_W<CTRL_SPEC> {
221 RESANDRES_W::new(self, 15)
222 }
223 #[doc = "Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low"]
224 #[inline(always)]
225 pub fn q_pol(&mut self) -> Q_POL_W<CTRL_SPEC> {
226 Q_POL_W::new(self, 18)
227 }
228 #[doc = "Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low"]
229 #[inline(always)]
230 pub fn d_pol(&mut self) -> D_POL_W<CTRL_SPEC> {
231 D_POL_W::new(self, 19)
232 }
233 #[doc = "Bit 20 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable."]
234 #[inline(always)]
235 pub fn fread_quad(&mut self) -> FREAD_QUAD_W<CTRL_SPEC> {
236 FREAD_QUAD_W::new(self, 20)
237 }
238 #[doc = "Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low."]
239 #[inline(always)]
240 pub fn wp(&mut self) -> WP_W<CTRL_SPEC> {
241 WP_W::new(self, 21)
242 }
243 #[doc = "Bit 22 - two bytes data will be written to status register when it is set. 1: enable 0: disable."]
244 #[inline(always)]
245 pub fn wrsr_2b(&mut self) -> WRSR_2B_W<CTRL_SPEC> {
246 WRSR_2B_W::new(self, 22)
247 }
248 #[doc = "Bit 23 - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable."]
249 #[inline(always)]
250 pub fn fread_dio(&mut self) -> FREAD_DIO_W<CTRL_SPEC> {
251 FREAD_DIO_W::new(self, 23)
252 }
253 #[doc = "Bit 24 - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable."]
254 #[inline(always)]
255 pub fn fread_qio(&mut self) -> FREAD_QIO_W<CTRL_SPEC> {
256 FREAD_QIO_W::new(self, 24)
257 }
258}
259#[doc = "SPI1 control register.\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
260pub struct CTRL_SPEC;
261impl crate::RegisterSpec for CTRL_SPEC {
262 type Ux = u32;
263}
264#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
265impl crate::Readable for CTRL_SPEC {}
266#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
267impl crate::Writable for CTRL_SPEC {
268 type Safety = crate::Unsafe;
269}
270#[doc = "`reset()` method sets CTRL to value 0x002c_a00c"]
271impl crate::Resettable for CTRL_SPEC {
272 const RESET_VALUE: u32 = 0x002c_a00c;
273}