esp32h2/spi1/
int_clr.rs

1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `PER_END` writer - The clear bit for SPI_MEM_PER_END_INT interrupt."]
4pub type PER_END_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `PES_END` writer - The clear bit for SPI_MEM_PES_END_INT interrupt."]
6pub type PES_END_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `WPE_END` writer - The clear bit for SPI_MEM_WPE_END_INT interrupt."]
8pub type WPE_END_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `SLV_ST_END` writer - The clear bit for SPI_MEM_SLV_ST_END_INT interrupt."]
10pub type SLV_ST_END_W<'a, REG> = crate::BitWriter1C<'a, REG>;
11#[doc = "Field `MST_ST_END` writer - The clear bit for SPI_MEM_MST_ST_END_INT interrupt."]
12pub type MST_ST_END_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `BROWN_OUT` writer - The status bit for SPI_MEM_BROWN_OUT_INT interrupt."]
14pub type BROWN_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
15#[cfg(feature = "impl-register-debug")]
16impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
17    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
18        write!(f, "(not readable)")
19    }
20}
21impl W {
22    #[doc = "Bit 0 - The clear bit for SPI_MEM_PER_END_INT interrupt."]
23    #[inline(always)]
24    pub fn per_end(&mut self) -> PER_END_W<INT_CLR_SPEC> {
25        PER_END_W::new(self, 0)
26    }
27    #[doc = "Bit 1 - The clear bit for SPI_MEM_PES_END_INT interrupt."]
28    #[inline(always)]
29    pub fn pes_end(&mut self) -> PES_END_W<INT_CLR_SPEC> {
30        PES_END_W::new(self, 1)
31    }
32    #[doc = "Bit 2 - The clear bit for SPI_MEM_WPE_END_INT interrupt."]
33    #[inline(always)]
34    pub fn wpe_end(&mut self) -> WPE_END_W<INT_CLR_SPEC> {
35        WPE_END_W::new(self, 2)
36    }
37    #[doc = "Bit 3 - The clear bit for SPI_MEM_SLV_ST_END_INT interrupt."]
38    #[inline(always)]
39    pub fn slv_st_end(&mut self) -> SLV_ST_END_W<INT_CLR_SPEC> {
40        SLV_ST_END_W::new(self, 3)
41    }
42    #[doc = "Bit 4 - The clear bit for SPI_MEM_MST_ST_END_INT interrupt."]
43    #[inline(always)]
44    pub fn mst_st_end(&mut self) -> MST_ST_END_W<INT_CLR_SPEC> {
45        MST_ST_END_W::new(self, 4)
46    }
47    #[doc = "Bit 10 - The status bit for SPI_MEM_BROWN_OUT_INT interrupt."]
48    #[inline(always)]
49    pub fn brown_out(&mut self) -> BROWN_OUT_W<INT_CLR_SPEC> {
50        BROWN_OUT_W::new(self, 10)
51    }
52}
53#[doc = "SPI1 interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
54pub struct INT_CLR_SPEC;
55impl crate::RegisterSpec for INT_CLR_SPEC {
56    type Ux = u32;
57}
58#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
59impl crate::Writable for INT_CLR_SPEC {
60    type Safety = crate::Unsafe;
61    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x041f;
62}
63#[doc = "`reset()` method sets INT_CLR to value 0"]
64impl crate::Resettable for INT_CLR_SPEC {}
esp32h2/spi1/int_clr.rs

esp32h2/spi1/
int_clr.rs
