esp32h2/spi0/
cache_sctrl.rs

1#[doc = "Register `CACHE_SCTRL` reader"]
2pub type R = crate::R<CACHE_SCTRL_SPEC>;
3#[doc = "Field `CACHE_USR_SADDR_4BYTE` reader - For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable."]
4pub type CACHE_USR_SADDR_4BYTE_R = crate::BitReader;
5#[doc = "Field `USR_SRAM_DIO` reader - For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable"]
6pub type USR_SRAM_DIO_R = crate::BitReader;
7#[doc = "Field `USR_SRAM_QIO` reader - For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable"]
8pub type USR_SRAM_QIO_R = crate::BitReader;
9#[doc = "Field `USR_WR_SRAM_DUMMY` reader - For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations."]
10pub type USR_WR_SRAM_DUMMY_R = crate::BitReader;
11#[doc = "Field `USR_RD_SRAM_DUMMY` reader - For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations."]
12pub type USR_RD_SRAM_DUMMY_R = crate::BitReader;
13#[doc = "Field `CACHE_SRAM_USR_RCMD` reader - For SPI0, In the external RAM mode cache read external RAM for user define command."]
14pub type CACHE_SRAM_USR_RCMD_R = crate::BitReader;
15#[doc = "Field `SRAM_RDUMMY_CYCLELEN` reader - For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1)."]
16pub type SRAM_RDUMMY_CYCLELEN_R = crate::FieldReader;
17#[doc = "Field `SRAM_ADDR_BITLEN` reader - For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1)."]
18pub type SRAM_ADDR_BITLEN_R = crate::FieldReader;
19#[doc = "Field `CACHE_SRAM_USR_WCMD` reader - For SPI0, In the external RAM mode cache write sram for user define command"]
20pub type CACHE_SRAM_USR_WCMD_R = crate::BitReader;
21#[doc = "Field `SRAM_OCT` reader - reserved"]
22pub type SRAM_OCT_R = crate::BitReader;
23#[doc = "Field `SRAM_WDUMMY_CYCLELEN` reader - For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1)."]
24pub type SRAM_WDUMMY_CYCLELEN_R = crate::FieldReader;
25impl R {
26    #[doc = "Bit 0 - For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable."]
27    #[inline(always)]
28    pub fn cache_usr_saddr_4byte(&self) -> CACHE_USR_SADDR_4BYTE_R {
29        CACHE_USR_SADDR_4BYTE_R::new((self.bits & 1) != 0)
30    }
31    #[doc = "Bit 1 - For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable"]
32    #[inline(always)]
33    pub fn usr_sram_dio(&self) -> USR_SRAM_DIO_R {
34        USR_SRAM_DIO_R::new(((self.bits >> 1) & 1) != 0)
35    }
36    #[doc = "Bit 2 - For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable"]
37    #[inline(always)]
38    pub fn usr_sram_qio(&self) -> USR_SRAM_QIO_R {
39        USR_SRAM_QIO_R::new(((self.bits >> 2) & 1) != 0)
40    }
41    #[doc = "Bit 3 - For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations."]
42    #[inline(always)]
43    pub fn usr_wr_sram_dummy(&self) -> USR_WR_SRAM_DUMMY_R {
44        USR_WR_SRAM_DUMMY_R::new(((self.bits >> 3) & 1) != 0)
45    }
46    #[doc = "Bit 4 - For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations."]
47    #[inline(always)]
48    pub fn usr_rd_sram_dummy(&self) -> USR_RD_SRAM_DUMMY_R {
49        USR_RD_SRAM_DUMMY_R::new(((self.bits >> 4) & 1) != 0)
50    }
51    #[doc = "Bit 5 - For SPI0, In the external RAM mode cache read external RAM for user define command."]
52    #[inline(always)]
53    pub fn cache_sram_usr_rcmd(&self) -> CACHE_SRAM_USR_RCMD_R {
54        CACHE_SRAM_USR_RCMD_R::new(((self.bits >> 5) & 1) != 0)
55    }
56    #[doc = "Bits 6:11 - For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1)."]
57    #[inline(always)]
58    pub fn sram_rdummy_cyclelen(&self) -> SRAM_RDUMMY_CYCLELEN_R {
59        SRAM_RDUMMY_CYCLELEN_R::new(((self.bits >> 6) & 0x3f) as u8)
60    }
61    #[doc = "Bits 14:19 - For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1)."]
62    #[inline(always)]
63    pub fn sram_addr_bitlen(&self) -> SRAM_ADDR_BITLEN_R {
64        SRAM_ADDR_BITLEN_R::new(((self.bits >> 14) & 0x3f) as u8)
65    }
66    #[doc = "Bit 20 - For SPI0, In the external RAM mode cache write sram for user define command"]
67    #[inline(always)]
68    pub fn cache_sram_usr_wcmd(&self) -> CACHE_SRAM_USR_WCMD_R {
69        CACHE_SRAM_USR_WCMD_R::new(((self.bits >> 20) & 1) != 0)
70    }
71    #[doc = "Bit 21 - reserved"]
72    #[inline(always)]
73    pub fn sram_oct(&self) -> SRAM_OCT_R {
74        SRAM_OCT_R::new(((self.bits >> 21) & 1) != 0)
75    }
76    #[doc = "Bits 22:27 - For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1)."]
77    #[inline(always)]
78    pub fn sram_wdummy_cyclelen(&self) -> SRAM_WDUMMY_CYCLELEN_R {
79        SRAM_WDUMMY_CYCLELEN_R::new(((self.bits >> 22) & 0x3f) as u8)
80    }
81}
82#[cfg(feature = "impl-register-debug")]
83impl core::fmt::Debug for R {
84    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
85        f.debug_struct("CACHE_SCTRL")
86            .field("cache_usr_saddr_4byte", &self.cache_usr_saddr_4byte())
87            .field("usr_sram_dio", &self.usr_sram_dio())
88            .field("usr_sram_qio", &self.usr_sram_qio())
89            .field("usr_wr_sram_dummy", &self.usr_wr_sram_dummy())
90            .field("usr_rd_sram_dummy", &self.usr_rd_sram_dummy())
91            .field("cache_sram_usr_rcmd", &self.cache_sram_usr_rcmd())
92            .field("sram_rdummy_cyclelen", &self.sram_rdummy_cyclelen())
93            .field("sram_addr_bitlen", &self.sram_addr_bitlen())
94            .field("cache_sram_usr_wcmd", &self.cache_sram_usr_wcmd())
95            .field("sram_oct", &self.sram_oct())
96            .field("sram_wdummy_cyclelen", &self.sram_wdummy_cyclelen())
97            .finish()
98    }
99}
100#[doc = "SPI0 external RAM control register\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_sctrl::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
101pub struct CACHE_SCTRL_SPEC;
102impl crate::RegisterSpec for CACHE_SCTRL_SPEC {
103    type Ux = u32;
104}
105#[doc = "`read()` method returns [`cache_sctrl::R`](R) reader structure"]
106impl crate::Readable for CACHE_SCTRL_SPEC {}
107#[doc = "`reset()` method sets CACHE_SCTRL to value 0x0055_c070"]
108impl crate::Resettable for CACHE_SCTRL_SPEC {
109    const RESET_VALUE: u32 = 0x0055_c070;
110}
esp32h2/spi0/cache_sctrl.rs

esp32h2/spi0/
cache_sctrl.rs
