esp32h2/i2s0/
rx_timing.rs

1#[doc = "Register `RX_TIMING` reader"]
2pub type R = crate::R<RX_TIMING_SPEC>;
3#[doc = "Register `RX_TIMING` writer"]
4pub type W = crate::W<RX_TIMING_SPEC>;
5#[doc = "Field `RX_SD_IN_DM` reader - The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
6pub type RX_SD_IN_DM_R = crate::FieldReader;
7#[doc = "Field `RX_SD_IN_DM` writer - The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
8pub type RX_SD_IN_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `RX_WS_OUT_DM` reader - The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
10pub type RX_WS_OUT_DM_R = crate::FieldReader;
11#[doc = "Field `RX_WS_OUT_DM` writer - The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
12pub type RX_WS_OUT_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `RX_BCK_OUT_DM` reader - The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
14pub type RX_BCK_OUT_DM_R = crate::FieldReader;
15#[doc = "Field `RX_BCK_OUT_DM` writer - The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
16pub type RX_BCK_OUT_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17#[doc = "Field `RX_WS_IN_DM` reader - The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
18pub type RX_WS_IN_DM_R = crate::FieldReader;
19#[doc = "Field `RX_WS_IN_DM` writer - The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
20pub type RX_WS_IN_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21#[doc = "Field `RX_BCK_IN_DM` reader - The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
22pub type RX_BCK_IN_DM_R = crate::FieldReader;
23#[doc = "Field `RX_BCK_IN_DM` writer - The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
24pub type RX_BCK_IN_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25impl R {
26    #[doc = "Bits 0:1 - The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
27    #[inline(always)]
28    pub fn rx_sd_in_dm(&self) -> RX_SD_IN_DM_R {
29        RX_SD_IN_DM_R::new((self.bits & 3) as u8)
30    }
31    #[doc = "Bits 16:17 - The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
32    #[inline(always)]
33    pub fn rx_ws_out_dm(&self) -> RX_WS_OUT_DM_R {
34        RX_WS_OUT_DM_R::new(((self.bits >> 16) & 3) as u8)
35    }
36    #[doc = "Bits 20:21 - The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
37    #[inline(always)]
38    pub fn rx_bck_out_dm(&self) -> RX_BCK_OUT_DM_R {
39        RX_BCK_OUT_DM_R::new(((self.bits >> 20) & 3) as u8)
40    }
41    #[doc = "Bits 24:25 - The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
42    #[inline(always)]
43    pub fn rx_ws_in_dm(&self) -> RX_WS_IN_DM_R {
44        RX_WS_IN_DM_R::new(((self.bits >> 24) & 3) as u8)
45    }
46    #[doc = "Bits 28:29 - The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
47    #[inline(always)]
48    pub fn rx_bck_in_dm(&self) -> RX_BCK_IN_DM_R {
49        RX_BCK_IN_DM_R::new(((self.bits >> 28) & 3) as u8)
50    }
51}
52#[cfg(feature = "impl-register-debug")]
53impl core::fmt::Debug for R {
54    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
55        f.debug_struct("RX_TIMING")
56            .field("rx_sd_in_dm", &self.rx_sd_in_dm())
57            .field("rx_ws_out_dm", &self.rx_ws_out_dm())
58            .field("rx_bck_out_dm", &self.rx_bck_out_dm())
59            .field("rx_ws_in_dm", &self.rx_ws_in_dm())
60            .field("rx_bck_in_dm", &self.rx_bck_in_dm())
61            .finish()
62    }
63}
64impl W {
65    #[doc = "Bits 0:1 - The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
66    #[inline(always)]
67    pub fn rx_sd_in_dm(&mut self) -> RX_SD_IN_DM_W<RX_TIMING_SPEC> {
68        RX_SD_IN_DM_W::new(self, 0)
69    }
70    #[doc = "Bits 16:17 - The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
71    #[inline(always)]
72    pub fn rx_ws_out_dm(&mut self) -> RX_WS_OUT_DM_W<RX_TIMING_SPEC> {
73        RX_WS_OUT_DM_W::new(self, 16)
74    }
75    #[doc = "Bits 20:21 - The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
76    #[inline(always)]
77    pub fn rx_bck_out_dm(&mut self) -> RX_BCK_OUT_DM_W<RX_TIMING_SPEC> {
78        RX_BCK_OUT_DM_W::new(self, 20)
79    }
80    #[doc = "Bits 24:25 - The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
81    #[inline(always)]
82    pub fn rx_ws_in_dm(&mut self) -> RX_WS_IN_DM_W<RX_TIMING_SPEC> {
83        RX_WS_IN_DM_W::new(self, 24)
84    }
85    #[doc = "Bits 28:29 - The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
86    #[inline(always)]
87    pub fn rx_bck_in_dm(&mut self) -> RX_BCK_IN_DM_W<RX_TIMING_SPEC> {
88        RX_BCK_IN_DM_W::new(self, 28)
89    }
90}
91#[doc = "I2S RX timing control register\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_timing::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_timing::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
92pub struct RX_TIMING_SPEC;
93impl crate::RegisterSpec for RX_TIMING_SPEC {
94    type Ux = u32;
95}
96#[doc = "`read()` method returns [`rx_timing::R`](R) reader structure"]
97impl crate::Readable for RX_TIMING_SPEC {}
98#[doc = "`write(|w| ..)` method takes [`rx_timing::W`](W) writer structure"]
99impl crate::Writable for RX_TIMING_SPEC {
100    type Safety = crate::Unsafe;
101}
102#[doc = "`reset()` method sets RX_TIMING to value 0"]
103impl crate::Resettable for RX_TIMING_SPEC {}
esp32h2/i2s0/rx_timing.rs

esp32h2/i2s0/
rx_timing.rs
