1#[repr(C)]
2#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
3#[doc = "Cluster CH%s, containing IN_CONF0_CH?, IN_CONF1_CH?, INFIFO_STATUS_CH?, IN_POP_CH?, IN_LINK_CH?, IN_STATE_CH?, IN_SUC_EOF_DES_ADDR_CH?, IN_ERR_EOF_DES_ADDR_CH?, IN_DSCR_CH?, IN_DSCR_BF0_CH?, IN_DSCR_BF1_CH?, IN_PRI_CH?, IN_PERI_SEL_CH?, OUT_CONF0_CH?, OUT_CONF1_CH?, OUTFIFO_STATUS_CH?, OUT_PUSH_CH?, OUT_LINK_CH?, OUT_STATE_CH?, OUT_EOF_DES_ADDR_CH?, OUT_EOF_BFR_DES_ADDR_CH?, OUT_DSCR_CH?, OUT_DSCR_BF0_CH?, OUT_DSCR_BF1_CH?, OUT_PRI_CH?, OUT_PERI_SEL_CH?"]
4pub struct CH {
5 in_conf0: IN_CONF0,
6 in_conf1: IN_CONF1,
7 infifo_status: INFIFO_STATUS,
8 in_pop: IN_POP,
9 in_link: IN_LINK,
10 in_state: IN_STATE,
11 in_suc_eof_des_addr: IN_SUC_EOF_DES_ADDR,
12 in_err_eof_des_addr: IN_ERR_EOF_DES_ADDR,
13 in_dscr: IN_DSCR,
14 in_dscr_bf0: IN_DSCR_BF0,
15 in_dscr_bf1: IN_DSCR_BF1,
16 in_pri: IN_PRI,
17 in_peri_sel: IN_PERI_SEL,
18 _reserved13: [u8; 0x2c],
19 out_conf0: OUT_CONF0,
20 out_conf1: OUT_CONF1,
21 outfifo_status: OUTFIFO_STATUS,
22 out_push: OUT_PUSH,
23 out_link: OUT_LINK,
24 out_state: OUT_STATE,
25 out_eof_des_addr: OUT_EOF_DES_ADDR,
26 out_eof_bfr_des_addr: OUT_EOF_BFR_DES_ADDR,
27 out_dscr: OUT_DSCR,
28 out_dscr_bf0: OUT_DSCR_BF0,
29 out_dscr_bf1: OUT_DSCR_BF1,
30 out_pri: OUT_PRI,
31 out_peri_sel: OUT_PERI_SEL,
32 _reserved_end: [u8; 0x2c],
33}
34impl CH {
35 #[doc = "0x00 - Configure 0 register of Rx channel 0"]
36 #[inline(always)]
37 pub const fn in_conf0(&self) -> &IN_CONF0 {
38 &self.in_conf0
39 }
40 #[doc = "0x04 - Configure 1 register of Rx channel 0"]
41 #[inline(always)]
42 pub const fn in_conf1(&self) -> &IN_CONF1 {
43 &self.in_conf1
44 }
45 #[doc = "0x08 - Receive FIFO status of Rx channel 0"]
46 #[inline(always)]
47 pub const fn infifo_status(&self) -> &INFIFO_STATUS {
48 &self.infifo_status
49 }
50 #[doc = "0x0c - Pop control register of Rx channel 0"]
51 #[inline(always)]
52 pub const fn in_pop(&self) -> &IN_POP {
53 &self.in_pop
54 }
55 #[doc = "0x10 - Link descriptor configure and control register of Rx channel 0"]
56 #[inline(always)]
57 pub const fn in_link(&self) -> &IN_LINK {
58 &self.in_link
59 }
60 #[doc = "0x14 - Receive status of Rx channel 0"]
61 #[inline(always)]
62 pub const fn in_state(&self) -> &IN_STATE {
63 &self.in_state
64 }
65 #[doc = "0x18 - Inlink descriptor address when EOF occurs of Rx channel 0"]
66 #[inline(always)]
67 pub const fn in_suc_eof_des_addr(&self) -> &IN_SUC_EOF_DES_ADDR {
68 &self.in_suc_eof_des_addr
69 }
70 #[doc = "0x1c - Inlink descriptor address when errors occur of Rx channel 0"]
71 #[inline(always)]
72 pub const fn in_err_eof_des_addr(&self) -> &IN_ERR_EOF_DES_ADDR {
73 &self.in_err_eof_des_addr
74 }
75 #[doc = "0x20 - Current inlink descriptor address of Rx channel 0"]
76 #[inline(always)]
77 pub const fn in_dscr(&self) -> &IN_DSCR {
78 &self.in_dscr
79 }
80 #[doc = "0x24 - The last inlink descriptor address of Rx channel 0"]
81 #[inline(always)]
82 pub const fn in_dscr_bf0(&self) -> &IN_DSCR_BF0 {
83 &self.in_dscr_bf0
84 }
85 #[doc = "0x28 - The second-to-last inlink descriptor address of Rx channel 0"]
86 #[inline(always)]
87 pub const fn in_dscr_bf1(&self) -> &IN_DSCR_BF1 {
88 &self.in_dscr_bf1
89 }
90 #[doc = "0x2c - Priority register of Rx channel 0"]
91 #[inline(always)]
92 pub const fn in_pri(&self) -> &IN_PRI {
93 &self.in_pri
94 }
95 #[doc = "0x30 - Peripheral selection of Rx channel 0"]
96 #[inline(always)]
97 pub const fn in_peri_sel(&self) -> &IN_PERI_SEL {
98 &self.in_peri_sel
99 }
100 #[doc = "0x60 - Configure 0 register of Tx channel 1"]
101 #[inline(always)]
102 pub const fn out_conf0(&self) -> &OUT_CONF0 {
103 &self.out_conf0
104 }
105 #[doc = "0x64 - Configure 1 register of Tx channel 0"]
106 #[inline(always)]
107 pub const fn out_conf1(&self) -> &OUT_CONF1 {
108 &self.out_conf1
109 }
110 #[doc = "0x68 - Transmit FIFO status of Tx channel 0"]
111 #[inline(always)]
112 pub const fn outfifo_status(&self) -> &OUTFIFO_STATUS {
113 &self.outfifo_status
114 }
115 #[doc = "0x6c - Push control register of Rx channel 0"]
116 #[inline(always)]
117 pub const fn out_push(&self) -> &OUT_PUSH {
118 &self.out_push
119 }
120 #[doc = "0x70 - Link descriptor configure and control register of Tx channel 0"]
121 #[inline(always)]
122 pub const fn out_link(&self) -> &OUT_LINK {
123 &self.out_link
124 }
125 #[doc = "0x74 - Transmit status of Tx channel 0"]
126 #[inline(always)]
127 pub const fn out_state(&self) -> &OUT_STATE {
128 &self.out_state
129 }
130 #[doc = "0x78 - Outlink descriptor address when EOF occurs of Tx channel 0"]
131 #[inline(always)]
132 pub const fn out_eof_des_addr(&self) -> &OUT_EOF_DES_ADDR {
133 &self.out_eof_des_addr
134 }
135 #[doc = "0x7c - The last outlink descriptor address when EOF occurs of Tx channel 0"]
136 #[inline(always)]
137 pub const fn out_eof_bfr_des_addr(&self) -> &OUT_EOF_BFR_DES_ADDR {
138 &self.out_eof_bfr_des_addr
139 }
140 #[doc = "0x80 - Current inlink descriptor address of Tx channel 0"]
141 #[inline(always)]
142 pub const fn out_dscr(&self) -> &OUT_DSCR {
143 &self.out_dscr
144 }
145 #[doc = "0x84 - The last inlink descriptor address of Tx channel 0"]
146 #[inline(always)]
147 pub const fn out_dscr_bf0(&self) -> &OUT_DSCR_BF0 {
148 &self.out_dscr_bf0
149 }
150 #[doc = "0x88 - The second-to-last inlink descriptor address of Tx channel 0"]
151 #[inline(always)]
152 pub const fn out_dscr_bf1(&self) -> &OUT_DSCR_BF1 {
153 &self.out_dscr_bf1
154 }
155 #[doc = "0x8c - Priority register of Tx channel 0."]
156 #[inline(always)]
157 pub const fn out_pri(&self) -> &OUT_PRI {
158 &self.out_pri
159 }
160 #[doc = "0x90 - Peripheral selection of Tx channel 0"]
161 #[inline(always)]
162 pub const fn out_peri_sel(&self) -> &OUT_PERI_SEL {
163 &self.out_peri_sel
164 }
165}
166#[doc = "IN_CONF0 (rw) register accessor: Configure 0 register of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_conf0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_conf0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_conf0`] module"]
167pub type IN_CONF0 = crate::Reg<in_conf0::IN_CONF0_SPEC>;
168#[doc = "Configure 0 register of Rx channel 0"]
169pub mod in_conf0;
170#[doc = "IN_CONF1 (rw) register accessor: Configure 1 register of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_conf1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_conf1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_conf1`] module"]
171pub type IN_CONF1 = crate::Reg<in_conf1::IN_CONF1_SPEC>;
172#[doc = "Configure 1 register of Rx channel 0"]
173pub mod in_conf1;
174#[doc = "INFIFO_STATUS (r) register accessor: Receive FIFO status of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`infifo_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@infifo_status`] module"]
175pub type INFIFO_STATUS = crate::Reg<infifo_status::INFIFO_STATUS_SPEC>;
176#[doc = "Receive FIFO status of Rx channel 0"]
177pub mod infifo_status;
178#[doc = "IN_POP (rw) register accessor: Pop control register of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_pop::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_pop::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_pop`] module"]
179pub type IN_POP = crate::Reg<in_pop::IN_POP_SPEC>;
180#[doc = "Pop control register of Rx channel 0"]
181pub mod in_pop;
182#[doc = "IN_LINK (rw) register accessor: Link descriptor configure and control register of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_link::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_link::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_link`] module"]
183pub type IN_LINK = crate::Reg<in_link::IN_LINK_SPEC>;
184#[doc = "Link descriptor configure and control register of Rx channel 0"]
185pub mod in_link;
186#[doc = "IN_STATE (r) register accessor: Receive status of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_state`] module"]
187pub type IN_STATE = crate::Reg<in_state::IN_STATE_SPEC>;
188#[doc = "Receive status of Rx channel 0"]
189pub mod in_state;
190#[doc = "IN_SUC_EOF_DES_ADDR (r) register accessor: Inlink descriptor address when EOF occurs of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_suc_eof_des_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_suc_eof_des_addr`] module"]
191pub type IN_SUC_EOF_DES_ADDR = crate::Reg<in_suc_eof_des_addr::IN_SUC_EOF_DES_ADDR_SPEC>;
192#[doc = "Inlink descriptor address when EOF occurs of Rx channel 0"]
193pub mod in_suc_eof_des_addr;
194#[doc = "IN_ERR_EOF_DES_ADDR (r) register accessor: Inlink descriptor address when errors occur of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_err_eof_des_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_err_eof_des_addr`] module"]
195pub type IN_ERR_EOF_DES_ADDR = crate::Reg<in_err_eof_des_addr::IN_ERR_EOF_DES_ADDR_SPEC>;
196#[doc = "Inlink descriptor address when errors occur of Rx channel 0"]
197pub mod in_err_eof_des_addr;
198#[doc = "IN_DSCR (r) register accessor: Current inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_dscr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_dscr`] module"]
199pub type IN_DSCR = crate::Reg<in_dscr::IN_DSCR_SPEC>;
200#[doc = "Current inlink descriptor address of Rx channel 0"]
201pub mod in_dscr;
202#[doc = "IN_DSCR_BF0 (r) register accessor: The last inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_dscr_bf0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_dscr_bf0`] module"]
203pub type IN_DSCR_BF0 = crate::Reg<in_dscr_bf0::IN_DSCR_BF0_SPEC>;
204#[doc = "The last inlink descriptor address of Rx channel 0"]
205pub mod in_dscr_bf0;
206#[doc = "IN_DSCR_BF1 (r) register accessor: The second-to-last inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_dscr_bf1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_dscr_bf1`] module"]
207pub type IN_DSCR_BF1 = crate::Reg<in_dscr_bf1::IN_DSCR_BF1_SPEC>;
208#[doc = "The second-to-last inlink descriptor address of Rx channel 0"]
209pub mod in_dscr_bf1;
210#[doc = "IN_PRI (rw) register accessor: Priority register of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_pri::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_pri::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_pri`] module"]
211pub type IN_PRI = crate::Reg<in_pri::IN_PRI_SPEC>;
212#[doc = "Priority register of Rx channel 0"]
213pub mod in_pri;
214#[doc = "IN_PERI_SEL (rw) register accessor: Peripheral selection of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_peri_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_peri_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_peri_sel`] module"]
215pub type IN_PERI_SEL = crate::Reg<in_peri_sel::IN_PERI_SEL_SPEC>;
216#[doc = "Peripheral selection of Rx channel 0"]
217pub mod in_peri_sel;
218#[doc = "OUT_CONF0 (rw) register accessor: Configure 0 register of Tx channel 1\n\nYou can [`read`](crate::Reg::read) this register and get [`out_conf0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out_conf0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_conf0`] module"]
219pub type OUT_CONF0 = crate::Reg<out_conf0::OUT_CONF0_SPEC>;
220#[doc = "Configure 0 register of Tx channel 1"]
221pub mod out_conf0;
222#[doc = "OUT_CONF1 (rw) register accessor: Configure 1 register of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_conf1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out_conf1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_conf1`] module"]
223pub type OUT_CONF1 = crate::Reg<out_conf1::OUT_CONF1_SPEC>;
224#[doc = "Configure 1 register of Tx channel 0"]
225pub mod out_conf1;
226#[doc = "OUTFIFO_STATUS (r) register accessor: Transmit FIFO status of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`outfifo_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@outfifo_status`] module"]
227pub type OUTFIFO_STATUS = crate::Reg<outfifo_status::OUTFIFO_STATUS_SPEC>;
228#[doc = "Transmit FIFO status of Tx channel 0"]
229pub mod outfifo_status;
230#[doc = "OUT_PUSH (rw) register accessor: Push control register of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_push::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out_push::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_push`] module"]
231pub type OUT_PUSH = crate::Reg<out_push::OUT_PUSH_SPEC>;
232#[doc = "Push control register of Rx channel 0"]
233pub mod out_push;
234#[doc = "OUT_LINK (rw) register accessor: Link descriptor configure and control register of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_link::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out_link::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_link`] module"]
235pub type OUT_LINK = crate::Reg<out_link::OUT_LINK_SPEC>;
236#[doc = "Link descriptor configure and control register of Tx channel 0"]
237pub mod out_link;
238#[doc = "OUT_STATE (r) register accessor: Transmit status of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_state`] module"]
239pub type OUT_STATE = crate::Reg<out_state::OUT_STATE_SPEC>;
240#[doc = "Transmit status of Tx channel 0"]
241pub mod out_state;
242#[doc = "OUT_EOF_DES_ADDR (r) register accessor: Outlink descriptor address when EOF occurs of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_eof_des_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_eof_des_addr`] module"]
243pub type OUT_EOF_DES_ADDR = crate::Reg<out_eof_des_addr::OUT_EOF_DES_ADDR_SPEC>;
244#[doc = "Outlink descriptor address when EOF occurs of Tx channel 0"]
245pub mod out_eof_des_addr;
246#[doc = "OUT_EOF_BFR_DES_ADDR (r) register accessor: The last outlink descriptor address when EOF occurs of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_eof_bfr_des_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_eof_bfr_des_addr`] module"]
247pub type OUT_EOF_BFR_DES_ADDR = crate::Reg<out_eof_bfr_des_addr::OUT_EOF_BFR_DES_ADDR_SPEC>;
248#[doc = "The last outlink descriptor address when EOF occurs of Tx channel 0"]
249pub mod out_eof_bfr_des_addr;
250#[doc = "OUT_DSCR (r) register accessor: Current inlink descriptor address of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_dscr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_dscr`] module"]
251pub type OUT_DSCR = crate::Reg<out_dscr::OUT_DSCR_SPEC>;
252#[doc = "Current inlink descriptor address of Tx channel 0"]
253pub mod out_dscr;
254#[doc = "OUT_DSCR_BF0 (r) register accessor: The last inlink descriptor address of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_dscr_bf0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_dscr_bf0`] module"]
255pub type OUT_DSCR_BF0 = crate::Reg<out_dscr_bf0::OUT_DSCR_BF0_SPEC>;
256#[doc = "The last inlink descriptor address of Tx channel 0"]
257pub mod out_dscr_bf0;
258#[doc = "OUT_DSCR_BF1 (r) register accessor: The second-to-last inlink descriptor address of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_dscr_bf1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_dscr_bf1`] module"]
259pub type OUT_DSCR_BF1 = crate::Reg<out_dscr_bf1::OUT_DSCR_BF1_SPEC>;
260#[doc = "The second-to-last inlink descriptor address of Tx channel 0"]
261pub mod out_dscr_bf1;
262#[doc = "OUT_PRI (rw) register accessor: Priority register of Tx channel 0.\n\nYou can [`read`](crate::Reg::read) this register and get [`out_pri::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out_pri::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_pri`] module"]
263pub type OUT_PRI = crate::Reg<out_pri::OUT_PRI_SPEC>;
264#[doc = "Priority register of Tx channel 0."]
265pub mod out_pri;
266#[doc = "OUT_PERI_SEL (rw) register accessor: Peripheral selection of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_peri_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out_peri_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_peri_sel`] module"]
267pub type OUT_PERI_SEL = crate::Reg<out_peri_sel::OUT_PERI_SEL_SPEC>;
268#[doc = "Peripheral selection of Tx channel 0"]
269pub mod out_peri_sel;