esp32h2/spi0/
misc.rs

1#[doc = "Register `MISC` reader"]
2pub type R = crate::R<MISC_SPEC>;
3#[doc = "Register `MISC` writer"]
4pub type W = crate::W<MISC_SPEC>;
5#[doc = "Field `FSUB_PIN` reader - For SPI0, flash is connected to SUBPINs."]
6pub type FSUB_PIN_R = crate::BitReader;
7#[doc = "Field `SSUB_PIN` reader - For SPI0, sram is connected to SUBPINs."]
8pub type SSUB_PIN_R = crate::BitReader;
9#[doc = "Field `CK_IDLE_EDGE` reader - 1: SPI_CLK line is high when idle 0: spi clk line is low when idle"]
10pub type CK_IDLE_EDGE_R = crate::BitReader;
11#[doc = "Field `CK_IDLE_EDGE` writer - 1: SPI_CLK line is high when idle 0: spi clk line is low when idle"]
12pub type CK_IDLE_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CS_KEEP_ACTIVE` reader - SPI_CS line keep low when the bit is set."]
14pub type CS_KEEP_ACTIVE_R = crate::BitReader;
15#[doc = "Field `CS_KEEP_ACTIVE` writer - SPI_CS line keep low when the bit is set."]
16pub type CS_KEEP_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    #[doc = "Bit 7 - For SPI0, flash is connected to SUBPINs."]
19    #[inline(always)]
20    pub fn fsub_pin(&self) -> FSUB_PIN_R {
21        FSUB_PIN_R::new(((self.bits >> 7) & 1) != 0)
22    }
23    #[doc = "Bit 8 - For SPI0, sram is connected to SUBPINs."]
24    #[inline(always)]
25    pub fn ssub_pin(&self) -> SSUB_PIN_R {
26        SSUB_PIN_R::new(((self.bits >> 8) & 1) != 0)
27    }
28    #[doc = "Bit 9 - 1: SPI_CLK line is high when idle 0: spi clk line is low when idle"]
29    #[inline(always)]
30    pub fn ck_idle_edge(&self) -> CK_IDLE_EDGE_R {
31        CK_IDLE_EDGE_R::new(((self.bits >> 9) & 1) != 0)
32    }
33    #[doc = "Bit 10 - SPI_CS line keep low when the bit is set."]
34    #[inline(always)]
35    pub fn cs_keep_active(&self) -> CS_KEEP_ACTIVE_R {
36        CS_KEEP_ACTIVE_R::new(((self.bits >> 10) & 1) != 0)
37    }
38}
39#[cfg(feature = "impl-register-debug")]
40impl core::fmt::Debug for R {
41    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
42        f.debug_struct("MISC")
43            .field("fsub_pin", &self.fsub_pin())
44            .field("ssub_pin", &self.ssub_pin())
45            .field("ck_idle_edge", &self.ck_idle_edge())
46            .field("cs_keep_active", &self.cs_keep_active())
47            .finish()
48    }
49}
50impl W {
51    #[doc = "Bit 9 - 1: SPI_CLK line is high when idle 0: spi clk line is low when idle"]
52    #[inline(always)]
53    pub fn ck_idle_edge(&mut self) -> CK_IDLE_EDGE_W<MISC_SPEC> {
54        CK_IDLE_EDGE_W::new(self, 9)
55    }
56    #[doc = "Bit 10 - SPI_CS line keep low when the bit is set."]
57    #[inline(always)]
58    pub fn cs_keep_active(&mut self) -> CS_KEEP_ACTIVE_W<MISC_SPEC> {
59        CS_KEEP_ACTIVE_W::new(self, 10)
60    }
61}
62#[doc = "SPI0 misc register\n\nYou can [`read`](crate::Reg::read) this register and get [`misc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`misc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
63pub struct MISC_SPEC;
64impl crate::RegisterSpec for MISC_SPEC {
65    type Ux = u32;
66}
67#[doc = "`read()` method returns [`misc::R`](R) reader structure"]
68impl crate::Readable for MISC_SPEC {}
69#[doc = "`write(|w| ..)` method takes [`misc::W`](W) writer structure"]
70impl crate::Writable for MISC_SPEC {
71    type Safety = crate::Unsafe;
72}
73#[doc = "`reset()` method sets MISC to value 0"]
74impl crate::Resettable for MISC_SPEC {}
esp32h2/spi0/misc.rs

esp32h2/spi0/
misc.rs
