1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `TIMER0_STOP` writer - Set this bit to clear the interrupt triggered when the timer 0 stops."]
4pub type TIMER0_STOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `TIMER1_STOP` writer - Set this bit to clear the interrupt triggered when the timer 1 stops."]
6pub type TIMER1_STOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `TIMER2_STOP` writer - Set this bit to clear the interrupt triggered when the timer 2 stops."]
8pub type TIMER2_STOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `TIMER0_TEZ` writer - Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event."]
10pub type TIMER0_TEZ_W<'a, REG> = crate::BitWriter1C<'a, REG>;
11#[doc = "Field `TIMER1_TEZ` writer - Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event."]
12pub type TIMER1_TEZ_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `TIMER2_TEZ` writer - Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event."]
14pub type TIMER2_TEZ_W<'a, REG> = crate::BitWriter1C<'a, REG>;
15#[doc = "Field `TIMER0_TEP` writer - Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event."]
16pub type TIMER0_TEP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
17#[doc = "Field `TIMER1_TEP` writer - Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event."]
18pub type TIMER1_TEP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
19#[doc = "Field `TIMER2_TEP` writer - Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event."]
20pub type TIMER2_TEP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
21#[doc = "Field `FAULT0` writer - Set this bit to clear the interrupt triggered when event_f0 starts."]
22pub type FAULT0_W<'a, REG> = crate::BitWriter1C<'a, REG>;
23#[doc = "Field `FAULT1` writer - Set this bit to clear the interrupt triggered when event_f1 starts."]
24pub type FAULT1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
25#[doc = "Field `FAULT2` writer - Set this bit to clear the interrupt triggered when event_f2 starts."]
26pub type FAULT2_W<'a, REG> = crate::BitWriter1C<'a, REG>;
27#[doc = "Field `FAULT0_CLR` writer - Set this bit to clear the interrupt triggered when event_f0 ends."]
28pub type FAULT0_CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
29#[doc = "Field `FAULT1_CLR` writer - Set this bit to clear the interrupt triggered when event_f1 ends."]
30pub type FAULT1_CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
31#[doc = "Field `FAULT2_CLR` writer - Set this bit to clear the interrupt triggered when event_f2 ends."]
32pub type FAULT2_CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
33#[doc = "Field `CMPR0_TEA` writer - Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event"]
34pub type CMPR0_TEA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
35#[doc = "Field `CMPR1_TEA` writer - Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event"]
36pub type CMPR1_TEA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
37#[doc = "Field `CMPR2_TEA` writer - Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event"]
38pub type CMPR2_TEA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
39#[doc = "Field `CMPR0_TEB` writer - Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event"]
40pub type CMPR0_TEB_W<'a, REG> = crate::BitWriter1C<'a, REG>;
41#[doc = "Field `CMPR1_TEB` writer - Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event"]
42pub type CMPR1_TEB_W<'a, REG> = crate::BitWriter1C<'a, REG>;
43#[doc = "Field `CMPR2_TEB` writer - Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event"]
44pub type CMPR2_TEB_W<'a, REG> = crate::BitWriter1C<'a, REG>;
45#[doc = "Field `TZ0_CBC` writer - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
46pub type TZ0_CBC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
47#[doc = "Field `TZ1_CBC` writer - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
48pub type TZ1_CBC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
49#[doc = "Field `TZ2_CBC` writer - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
50pub type TZ2_CBC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
51#[doc = "Field `TZ0_OST` writer - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0."]
52pub type TZ0_OST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
53#[doc = "Field `TZ1_OST` writer - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1."]
54pub type TZ1_OST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
55#[doc = "Field `TZ2_OST` writer - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2."]
56pub type TZ2_OST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
57#[doc = "Field `CAP0` writer - Set this bit to clear the interrupt triggered by capture on channel 0."]
58pub type CAP0_W<'a, REG> = crate::BitWriter1C<'a, REG>;
59#[doc = "Field `CAP1` writer - Set this bit to clear the interrupt triggered by capture on channel 1."]
60pub type CAP1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
61#[doc = "Field `CAP2` writer - Set this bit to clear the interrupt triggered by capture on channel 2."]
62pub type CAP2_W<'a, REG> = crate::BitWriter1C<'a, REG>;
63#[cfg(feature = "impl-register-debug")]
64impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
65 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
66 write!(f, "(not readable)")
67 }
68}
69impl W {
70 #[doc = "Bit 0 - Set this bit to clear the interrupt triggered when the timer 0 stops."]
71 #[inline(always)]
72 pub fn timer0_stop(&mut self) -> TIMER0_STOP_W<INT_CLR_SPEC> {
73 TIMER0_STOP_W::new(self, 0)
74 }
75 #[doc = "Bit 1 - Set this bit to clear the interrupt triggered when the timer 1 stops."]
76 #[inline(always)]
77 pub fn timer1_stop(&mut self) -> TIMER1_STOP_W<INT_CLR_SPEC> {
78 TIMER1_STOP_W::new(self, 1)
79 }
80 #[doc = "Bit 2 - Set this bit to clear the interrupt triggered when the timer 2 stops."]
81 #[inline(always)]
82 pub fn timer2_stop(&mut self) -> TIMER2_STOP_W<INT_CLR_SPEC> {
83 TIMER2_STOP_W::new(self, 2)
84 }
85 #[doc = "Bit 3 - Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event."]
86 #[inline(always)]
87 pub fn timer0_tez(&mut self) -> TIMER0_TEZ_W<INT_CLR_SPEC> {
88 TIMER0_TEZ_W::new(self, 3)
89 }
90 #[doc = "Bit 4 - Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event."]
91 #[inline(always)]
92 pub fn timer1_tez(&mut self) -> TIMER1_TEZ_W<INT_CLR_SPEC> {
93 TIMER1_TEZ_W::new(self, 4)
94 }
95 #[doc = "Bit 5 - Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event."]
96 #[inline(always)]
97 pub fn timer2_tez(&mut self) -> TIMER2_TEZ_W<INT_CLR_SPEC> {
98 TIMER2_TEZ_W::new(self, 5)
99 }
100 #[doc = "Bit 6 - Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event."]
101 #[inline(always)]
102 pub fn timer0_tep(&mut self) -> TIMER0_TEP_W<INT_CLR_SPEC> {
103 TIMER0_TEP_W::new(self, 6)
104 }
105 #[doc = "Bit 7 - Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event."]
106 #[inline(always)]
107 pub fn timer1_tep(&mut self) -> TIMER1_TEP_W<INT_CLR_SPEC> {
108 TIMER1_TEP_W::new(self, 7)
109 }
110 #[doc = "Bit 8 - Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event."]
111 #[inline(always)]
112 pub fn timer2_tep(&mut self) -> TIMER2_TEP_W<INT_CLR_SPEC> {
113 TIMER2_TEP_W::new(self, 8)
114 }
115 #[doc = "Bit 9 - Set this bit to clear the interrupt triggered when event_f0 starts."]
116 #[inline(always)]
117 pub fn fault0(&mut self) -> FAULT0_W<INT_CLR_SPEC> {
118 FAULT0_W::new(self, 9)
119 }
120 #[doc = "Bit 10 - Set this bit to clear the interrupt triggered when event_f1 starts."]
121 #[inline(always)]
122 pub fn fault1(&mut self) -> FAULT1_W<INT_CLR_SPEC> {
123 FAULT1_W::new(self, 10)
124 }
125 #[doc = "Bit 11 - Set this bit to clear the interrupt triggered when event_f2 starts."]
126 #[inline(always)]
127 pub fn fault2(&mut self) -> FAULT2_W<INT_CLR_SPEC> {
128 FAULT2_W::new(self, 11)
129 }
130 #[doc = "Bit 12 - Set this bit to clear the interrupt triggered when event_f0 ends."]
131 #[inline(always)]
132 pub fn fault0_clr(&mut self) -> FAULT0_CLR_W<INT_CLR_SPEC> {
133 FAULT0_CLR_W::new(self, 12)
134 }
135 #[doc = "Bit 13 - Set this bit to clear the interrupt triggered when event_f1 ends."]
136 #[inline(always)]
137 pub fn fault1_clr(&mut self) -> FAULT1_CLR_W<INT_CLR_SPEC> {
138 FAULT1_CLR_W::new(self, 13)
139 }
140 #[doc = "Bit 14 - Set this bit to clear the interrupt triggered when event_f2 ends."]
141 #[inline(always)]
142 pub fn fault2_clr(&mut self) -> FAULT2_CLR_W<INT_CLR_SPEC> {
143 FAULT2_CLR_W::new(self, 14)
144 }
145 #[doc = "Bit 15 - Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event"]
146 #[inline(always)]
147 pub fn cmpr0_tea(&mut self) -> CMPR0_TEA_W<INT_CLR_SPEC> {
148 CMPR0_TEA_W::new(self, 15)
149 }
150 #[doc = "Bit 16 - Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event"]
151 #[inline(always)]
152 pub fn cmpr1_tea(&mut self) -> CMPR1_TEA_W<INT_CLR_SPEC> {
153 CMPR1_TEA_W::new(self, 16)
154 }
155 #[doc = "Bit 17 - Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event"]
156 #[inline(always)]
157 pub fn cmpr2_tea(&mut self) -> CMPR2_TEA_W<INT_CLR_SPEC> {
158 CMPR2_TEA_W::new(self, 17)
159 }
160 #[doc = "Bit 18 - Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event"]
161 #[inline(always)]
162 pub fn cmpr0_teb(&mut self) -> CMPR0_TEB_W<INT_CLR_SPEC> {
163 CMPR0_TEB_W::new(self, 18)
164 }
165 #[doc = "Bit 19 - Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event"]
166 #[inline(always)]
167 pub fn cmpr1_teb(&mut self) -> CMPR1_TEB_W<INT_CLR_SPEC> {
168 CMPR1_TEB_W::new(self, 19)
169 }
170 #[doc = "Bit 20 - Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event"]
171 #[inline(always)]
172 pub fn cmpr2_teb(&mut self) -> CMPR2_TEB_W<INT_CLR_SPEC> {
173 CMPR2_TEB_W::new(self, 20)
174 }
175 #[doc = "Bit 21 - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
176 #[inline(always)]
177 pub fn tz0_cbc(&mut self) -> TZ0_CBC_W<INT_CLR_SPEC> {
178 TZ0_CBC_W::new(self, 21)
179 }
180 #[doc = "Bit 22 - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
181 #[inline(always)]
182 pub fn tz1_cbc(&mut self) -> TZ1_CBC_W<INT_CLR_SPEC> {
183 TZ1_CBC_W::new(self, 22)
184 }
185 #[doc = "Bit 23 - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
186 #[inline(always)]
187 pub fn tz2_cbc(&mut self) -> TZ2_CBC_W<INT_CLR_SPEC> {
188 TZ2_CBC_W::new(self, 23)
189 }
190 #[doc = "Bit 24 - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0."]
191 #[inline(always)]
192 pub fn tz0_ost(&mut self) -> TZ0_OST_W<INT_CLR_SPEC> {
193 TZ0_OST_W::new(self, 24)
194 }
195 #[doc = "Bit 25 - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1."]
196 #[inline(always)]
197 pub fn tz1_ost(&mut self) -> TZ1_OST_W<INT_CLR_SPEC> {
198 TZ1_OST_W::new(self, 25)
199 }
200 #[doc = "Bit 26 - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2."]
201 #[inline(always)]
202 pub fn tz2_ost(&mut self) -> TZ2_OST_W<INT_CLR_SPEC> {
203 TZ2_OST_W::new(self, 26)
204 }
205 #[doc = "Bit 27 - Set this bit to clear the interrupt triggered by capture on channel 0."]
206 #[inline(always)]
207 pub fn cap0(&mut self) -> CAP0_W<INT_CLR_SPEC> {
208 CAP0_W::new(self, 27)
209 }
210 #[doc = "Bit 28 - Set this bit to clear the interrupt triggered by capture on channel 1."]
211 #[inline(always)]
212 pub fn cap1(&mut self) -> CAP1_W<INT_CLR_SPEC> {
213 CAP1_W::new(self, 28)
214 }
215 #[doc = "Bit 29 - Set this bit to clear the interrupt triggered by capture on channel 2."]
216 #[inline(always)]
217 pub fn cap2(&mut self) -> CAP2_W<INT_CLR_SPEC> {
218 CAP2_W::new(self, 29)
219 }
220}
221#[doc = "Interrupt clear bits\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
222pub struct INT_CLR_SPEC;
223impl crate::RegisterSpec for INT_CLR_SPEC {
224 type Ux = u32;
225}
226#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
227impl crate::Writable for INT_CLR_SPEC {
228 type Safety = crate::Unsafe;
229 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
230 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3fff_ffff;
231}
232#[doc = "`reset()` method sets INT_CLR to value 0"]
233impl crate::Resettable for INT_CLR_SPEC {
234 const RESET_VALUE: u32 = 0;
235}