Module trace

RISC-V Trace Encoder

Modules

clock_gate

Clock gate control register

date

Version control register

fifo_status

fifo status register

intr_clr

interrupt clear register

intr_ena

interrupt enable register

intr_raw

interrupt status register

mem_addr_update

mem addr update

mem_current_addr

mem current addr

mem_end_addr

mem end addr

mem_start_addr

mem start addr

resync_prolonged

resync configuration register

trigger

trigger register

Structs

RegisterBlock

Register block

Type Aliases

CLOCK_GATE

CLOCK_GATE (rw) register accessor: Clock gate control register

DATE

DATE (rw) register accessor: Version control register

FIFO_STATUS

FIFO_STATUS (r) register accessor: fifo status register

INTR_CLR

INTR_CLR (w) register accessor: interrupt clear register

INTR_ENA

INTR_ENA (rw) register accessor: interrupt enable register

INTR_RAW

INTR_RAW (r) register accessor: interrupt status register

MEM_ADDR_UPDATE

MEM_ADDR_UPDATE (w) register accessor: mem addr update

MEM_CURRENT_ADDR

MEM_CURRENT_ADDR (r) register accessor: mem current addr

MEM_END_ADDR

MEM_END_ADDR (rw) register accessor: mem end addr

MEM_START_ADDR

MEM_START_ADDR (rw) register accessor: mem start addr

RESYNC_PROLONGED

RESYNC_PROLONGED (rw) register accessor: resync configuration register

TRIGGER

TRIGGER (rw) register accessor: trigger register