1#[doc = "Register `SLAVE` reader"]
2pub type R = crate::R<SLAVE_SPEC>;
3#[doc = "Register `SLAVE` writer"]
4pub type W = crate::W<SLAVE_SPEC>;
5#[doc = "Field `CLK_MODE` reader - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state."]
6pub type CLK_MODE_R = crate::FieldReader;
7#[doc = "Field `CLK_MODE` writer - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state."]
8pub type CLK_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `CLK_MODE_13` reader - {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B\\[0\\]/B\\[7\\]. 0: support spi clk mode 0 and 2, first edge output data B\\[1\\]/B\\[6\\]."]
10pub type CLK_MODE_13_R = crate::BitReader;
11#[doc = "Field `CLK_MODE_13` writer - {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B\\[0\\]/B\\[7\\]. 0: support spi clk mode 0 and 2, first edge output data B\\[1\\]/B\\[6\\]."]
12pub type CLK_MODE_13_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `RSCK_DATA_OUT` reader - It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge"]
14pub type RSCK_DATA_OUT_R = crate::BitReader;
15#[doc = "Field `RSCK_DATA_OUT` writer - It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge"]
16pub type RSCK_DATA_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SLV_RDDMA_BITLEN_EN` reader - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others"]
18pub type SLV_RDDMA_BITLEN_EN_R = crate::BitReader;
19#[doc = "Field `SLV_RDDMA_BITLEN_EN` writer - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others"]
20pub type SLV_RDDMA_BITLEN_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `SLV_WRDMA_BITLEN_EN` reader - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others"]
22pub type SLV_WRDMA_BITLEN_EN_R = crate::BitReader;
23#[doc = "Field `SLV_WRDMA_BITLEN_EN` writer - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others"]
24pub type SLV_WRDMA_BITLEN_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `SLV_RDBUF_BITLEN_EN` reader - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others"]
26pub type SLV_RDBUF_BITLEN_EN_R = crate::BitReader;
27#[doc = "Field `SLV_RDBUF_BITLEN_EN` writer - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others"]
28pub type SLV_RDBUF_BITLEN_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `SLV_WRBUF_BITLEN_EN` reader - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others"]
30pub type SLV_WRBUF_BITLEN_EN_R = crate::BitReader;
31#[doc = "Field `SLV_WRBUF_BITLEN_EN` writer - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others"]
32pub type SLV_WRBUF_BITLEN_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `DMA_SEG_MAGIC_VALUE` reader - The magic value of BM table in master DMA seg-trans."]
34pub type DMA_SEG_MAGIC_VALUE_R = crate::FieldReader;
35#[doc = "Field `DMA_SEG_MAGIC_VALUE` writer - The magic value of BM table in master DMA seg-trans."]
36pub type DMA_SEG_MAGIC_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
37#[doc = "Field `MODE` reader - Set SPI work mode. 1: slave mode 0: master mode."]
38pub type MODE_R = crate::BitReader;
39#[doc = "Field `MODE` writer - Set SPI work mode. 1: slave mode 0: master mode."]
40pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `SOFT_RESET` writer - Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state."]
42pub type SOFT_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
43#[doc = "Field `USR_CONF` reader - 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode."]
44pub type USR_CONF_R = crate::BitReader;
45#[doc = "Field `USR_CONF` writer - 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode."]
46pub type USR_CONF_W<'a, REG> = crate::BitWriter<'a, REG>;
47#[doc = "Field `MST_FD_WAIT_DMA_TX_DATA` reader - In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer."]
48pub type MST_FD_WAIT_DMA_TX_DATA_R = crate::BitReader;
49#[doc = "Field `MST_FD_WAIT_DMA_TX_DATA` writer - In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer."]
50pub type MST_FD_WAIT_DMA_TX_DATA_W<'a, REG> = crate::BitWriter<'a, REG>;
51impl R {
52 #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state."]
53 #[inline(always)]
54 pub fn clk_mode(&self) -> CLK_MODE_R {
55 CLK_MODE_R::new((self.bits & 3) as u8)
56 }
57 #[doc = "Bit 2 - {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B\\[0\\]/B\\[7\\]. 0: support spi clk mode 0 and 2, first edge output data B\\[1\\]/B\\[6\\]."]
58 #[inline(always)]
59 pub fn clk_mode_13(&self) -> CLK_MODE_13_R {
60 CLK_MODE_13_R::new(((self.bits >> 2) & 1) != 0)
61 }
62 #[doc = "Bit 3 - It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge"]
63 #[inline(always)]
64 pub fn rsck_data_out(&self) -> RSCK_DATA_OUT_R {
65 RSCK_DATA_OUT_R::new(((self.bits >> 3) & 1) != 0)
66 }
67 #[doc = "Bit 8 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others"]
68 #[inline(always)]
69 pub fn slv_rddma_bitlen_en(&self) -> SLV_RDDMA_BITLEN_EN_R {
70 SLV_RDDMA_BITLEN_EN_R::new(((self.bits >> 8) & 1) != 0)
71 }
72 #[doc = "Bit 9 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others"]
73 #[inline(always)]
74 pub fn slv_wrdma_bitlen_en(&self) -> SLV_WRDMA_BITLEN_EN_R {
75 SLV_WRDMA_BITLEN_EN_R::new(((self.bits >> 9) & 1) != 0)
76 }
77 #[doc = "Bit 10 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others"]
78 #[inline(always)]
79 pub fn slv_rdbuf_bitlen_en(&self) -> SLV_RDBUF_BITLEN_EN_R {
80 SLV_RDBUF_BITLEN_EN_R::new(((self.bits >> 10) & 1) != 0)
81 }
82 #[doc = "Bit 11 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others"]
83 #[inline(always)]
84 pub fn slv_wrbuf_bitlen_en(&self) -> SLV_WRBUF_BITLEN_EN_R {
85 SLV_WRBUF_BITLEN_EN_R::new(((self.bits >> 11) & 1) != 0)
86 }
87 #[doc = "Bits 22:25 - The magic value of BM table in master DMA seg-trans."]
88 #[inline(always)]
89 pub fn dma_seg_magic_value(&self) -> DMA_SEG_MAGIC_VALUE_R {
90 DMA_SEG_MAGIC_VALUE_R::new(((self.bits >> 22) & 0x0f) as u8)
91 }
92 #[doc = "Bit 26 - Set SPI work mode. 1: slave mode 0: master mode."]
93 #[inline(always)]
94 pub fn mode(&self) -> MODE_R {
95 MODE_R::new(((self.bits >> 26) & 1) != 0)
96 }
97 #[doc = "Bit 28 - 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode."]
98 #[inline(always)]
99 pub fn usr_conf(&self) -> USR_CONF_R {
100 USR_CONF_R::new(((self.bits >> 28) & 1) != 0)
101 }
102 #[doc = "Bit 29 - In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer."]
103 #[inline(always)]
104 pub fn mst_fd_wait_dma_tx_data(&self) -> MST_FD_WAIT_DMA_TX_DATA_R {
105 MST_FD_WAIT_DMA_TX_DATA_R::new(((self.bits >> 29) & 1) != 0)
106 }
107}
108#[cfg(feature = "impl-register-debug")]
109impl core::fmt::Debug for R {
110 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
111 f.debug_struct("SLAVE")
112 .field("clk_mode", &self.clk_mode())
113 .field("clk_mode_13", &self.clk_mode_13())
114 .field("rsck_data_out", &self.rsck_data_out())
115 .field("slv_rddma_bitlen_en", &self.slv_rddma_bitlen_en())
116 .field("slv_wrdma_bitlen_en", &self.slv_wrdma_bitlen_en())
117 .field("slv_rdbuf_bitlen_en", &self.slv_rdbuf_bitlen_en())
118 .field("slv_wrbuf_bitlen_en", &self.slv_wrbuf_bitlen_en())
119 .field("dma_seg_magic_value", &self.dma_seg_magic_value())
120 .field("mode", &self.mode())
121 .field("usr_conf", &self.usr_conf())
122 .field("mst_fd_wait_dma_tx_data", &self.mst_fd_wait_dma_tx_data())
123 .finish()
124 }
125}
126impl W {
127 #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state."]
128 #[inline(always)]
129 pub fn clk_mode(&mut self) -> CLK_MODE_W<SLAVE_SPEC> {
130 CLK_MODE_W::new(self, 0)
131 }
132 #[doc = "Bit 2 - {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B\\[0\\]/B\\[7\\]. 0: support spi clk mode 0 and 2, first edge output data B\\[1\\]/B\\[6\\]."]
133 #[inline(always)]
134 pub fn clk_mode_13(&mut self) -> CLK_MODE_13_W<SLAVE_SPEC> {
135 CLK_MODE_13_W::new(self, 2)
136 }
137 #[doc = "Bit 3 - It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge"]
138 #[inline(always)]
139 pub fn rsck_data_out(&mut self) -> RSCK_DATA_OUT_W<SLAVE_SPEC> {
140 RSCK_DATA_OUT_W::new(self, 3)
141 }
142 #[doc = "Bit 8 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others"]
143 #[inline(always)]
144 pub fn slv_rddma_bitlen_en(&mut self) -> SLV_RDDMA_BITLEN_EN_W<SLAVE_SPEC> {
145 SLV_RDDMA_BITLEN_EN_W::new(self, 8)
146 }
147 #[doc = "Bit 9 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others"]
148 #[inline(always)]
149 pub fn slv_wrdma_bitlen_en(&mut self) -> SLV_WRDMA_BITLEN_EN_W<SLAVE_SPEC> {
150 SLV_WRDMA_BITLEN_EN_W::new(self, 9)
151 }
152 #[doc = "Bit 10 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others"]
153 #[inline(always)]
154 pub fn slv_rdbuf_bitlen_en(&mut self) -> SLV_RDBUF_BITLEN_EN_W<SLAVE_SPEC> {
155 SLV_RDBUF_BITLEN_EN_W::new(self, 10)
156 }
157 #[doc = "Bit 11 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others"]
158 #[inline(always)]
159 pub fn slv_wrbuf_bitlen_en(&mut self) -> SLV_WRBUF_BITLEN_EN_W<SLAVE_SPEC> {
160 SLV_WRBUF_BITLEN_EN_W::new(self, 11)
161 }
162 #[doc = "Bits 22:25 - The magic value of BM table in master DMA seg-trans."]
163 #[inline(always)]
164 pub fn dma_seg_magic_value(&mut self) -> DMA_SEG_MAGIC_VALUE_W<SLAVE_SPEC> {
165 DMA_SEG_MAGIC_VALUE_W::new(self, 22)
166 }
167 #[doc = "Bit 26 - Set SPI work mode. 1: slave mode 0: master mode."]
168 #[inline(always)]
169 pub fn mode(&mut self) -> MODE_W<SLAVE_SPEC> {
170 MODE_W::new(self, 26)
171 }
172 #[doc = "Bit 27 - Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state."]
173 #[inline(always)]
174 pub fn soft_reset(&mut self) -> SOFT_RESET_W<SLAVE_SPEC> {
175 SOFT_RESET_W::new(self, 27)
176 }
177 #[doc = "Bit 28 - 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode."]
178 #[inline(always)]
179 pub fn usr_conf(&mut self) -> USR_CONF_W<SLAVE_SPEC> {
180 USR_CONF_W::new(self, 28)
181 }
182 #[doc = "Bit 29 - In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer."]
183 #[inline(always)]
184 pub fn mst_fd_wait_dma_tx_data(&mut self) -> MST_FD_WAIT_DMA_TX_DATA_W<SLAVE_SPEC> {
185 MST_FD_WAIT_DMA_TX_DATA_W::new(self, 29)
186 }
187}
188#[doc = "SPI slave control register\n\nYou can [`read`](crate::Reg::read) this register and get [`slave::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slave::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
189pub struct SLAVE_SPEC;
190impl crate::RegisterSpec for SLAVE_SPEC {
191 type Ux = u32;
192}
193#[doc = "`read()` method returns [`slave::R`](R) reader structure"]
194impl crate::Readable for SLAVE_SPEC {}
195#[doc = "`write(|w| ..)` method takes [`slave::W`](W) writer structure"]
196impl crate::Writable for SLAVE_SPEC {
197 type Safety = crate::Unsafe;
198 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
199 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
200}
201#[doc = "`reset()` method sets SLAVE to value 0x0280_0000"]
202impl crate::Resettable for SLAVE_SPEC {
203 const RESET_VALUE: u32 = 0x0280_0000;
204}