esp32h2::spi0

Module cache_sctrl

Source
Expand description

SPI0 external RAM control register

Structs§

Type Aliases§

  • CACHE_SRAM_USR_RCMD_R
    Field CACHE_SRAM_USR_RCMD reader - For SPI0, In the external RAM mode cache read external RAM for user define command.
  • CACHE_SRAM_USR_WCMD_R
    Field CACHE_SRAM_USR_WCMD reader - For SPI0, In the external RAM mode cache write sram for user define command
  • CACHE_USR_SADDR_4BYTE_R
    Field CACHE_USR_SADDR_4BYTE reader - For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable.
  • R
    Register CACHE_SCTRL reader
  • SRAM_ADDR_BITLEN_R
    Field SRAM_ADDR_BITLEN reader - For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1).
  • SRAM_OCT_R
    Field SRAM_OCT reader - reserved
  • SRAM_RDUMMY_CYCLELEN_R
    Field SRAM_RDUMMY_CYCLELEN reader - For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1).
  • SRAM_WDUMMY_CYCLELEN_R
    Field SRAM_WDUMMY_CYCLELEN reader - For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1).
  • USR_RD_SRAM_DUMMY_R
    Field USR_RD_SRAM_DUMMY reader - For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations.
  • USR_SRAM_DIO_R
    Field USR_SRAM_DIO reader - For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable
  • USR_SRAM_QIO_R
    Field USR_SRAM_QIO reader - For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable
  • USR_WR_SRAM_DUMMY_R
    Field USR_WR_SRAM_DUMMY reader - For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations.