Module esp32h2_hal::parl_io
source · Expand description
§Parallel IO
§Overview
The Parallel IO peripheral is a general purpose parallel interface that can be used to connect to external devices such as LED matrix, LCD display, Printer and Camera. The peripheral has independent TX and RX units. Each unit can have up to 8 or 16 data signals (depending on your target hardware) plus 1 or 2 clock signals.
The driver uses DMA (Direct Memory Access) for efficient data transfer.
§Examples
§Initialization for TX
// configure the data pins to use
let tx_pins = TxFourBits::new(io.pins.gpio1, io.pins.gpio2, io.pins.gpio3, io.pins.gpio4);
// configure the valid pin which will be driven high during a TX transfer
let pin_conf = TxPinConfigWithValidPin::new(tx_pins, io.pins.gpio5);
let mut parl_io = ParlIoTxOnly::new(
peripherals.PARL_IO,
dma_channel.configure(
false,
&mut tx_descriptors,
&mut rx_descriptors,
DmaPriority::Priority0,
),
1u32.MHz(),
&clocks,
)
.unwrap();
// configure a pin for the clock signal
let cp = ClkOutPin::new(io.pins.gpio6);
let mut parl_io_tx = parl_io
.tx
.with_config(pin_conf, cp, 0, SampleEdge::Normal, BitPackOrder::Msb)
.unwrap();
§Start TX transfer
let transfer = parl_io_tx.write_dma(buffer).unwrap();
// the buffer and driver is moved into the transfer and we can get it back via
// `wait`
(buffer, parl_io_tx) = transfer.wait().unwrap();
§Initialization for RX
let rx_pins = RxFourBits::new(io.pins.gpio1, io.pins.gpio2, io.pins.gpio3, io.pins.gpio4);
let parl_io = ParlIoRxOnly::new(
peripherals.PARL_IO,
dma_channel.configure(
false,
&mut tx_descriptors,
&mut rx_descriptors,
DmaPriority::Priority0,
),
1u32.MHz(),
&clocks,
)
.unwrap();
let mut parl_io_rx = parl_io
.rx
.with_config(rx_pins, NoClkPin, BitPackOrder::Msb, Some(0xfff))
.unwrap();
§Start RX transfer
let transfer = parl_io_rx.read_dma(buffer).unwrap();
// the buffer and driver is moved into the transfer and we can get it back via
// `wait`
(buffer, parl_io_rx) = transfer.wait().unwrap();
Structs§
- Wraps a GPIO pin which will be used as the TX clock input signal
- Wraps a GPIO pin which will be used as the clock output signal
- An in-progress DMA transfer.
- Used to configure no pin as clock output
- Parallel IO in full duplex mode
- Parallel IO RX channel
- Parallel IO in half duplex / RX only mode
- Parallel IO TX channel
- Parallel IO in half duplex / TX only mode
- Wraps a GPIO pin which will be used as the RX clock input signal
- An in-progress DMA transfer.
- Data pin configuration for 8 bit input mode
- Data pin configuration for 4 bit input mode
- Data pin configuration for 1 bit input mode
- Pin configuration where the pin for the valid signal is the MSB pin.
- Pin configuration with an additional pin for the valid signal.
- Data pin configuration for 2 bit input mode
- Data pin configuration for 8 bit output mode
- Data pin configuration for 4 bit output mode
- Data pin configuration for 1 bit output mode
- Pin configuration where the pin for the valid signal is the MSB pin.
- Pin configuration with an additional pin for the valid signal.
- Data pin configuration for 2 bit output mode
Enums§
- Parallel IO bit packing order
- Enable Mode
- Generation of GDMA SUC EOF
- Parallel IO errors
- Parallel IO sample edge