esp32c6/uart0/
clkdiv.rs

1#[doc = "Register `CLKDIV` reader"]
2pub type R = crate::R<CLKDIV_SPEC>;
3#[doc = "Register `CLKDIV` writer"]
4pub type W = crate::W<CLKDIV_SPEC>;
5#[doc = "Field `CLKDIV` reader - The integral part of the frequency divider factor."]
6pub type CLKDIV_R = crate::FieldReader<u16>;
7#[doc = "Field `CLKDIV` writer - The integral part of the frequency divider factor."]
8pub type CLKDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
9#[doc = "Field `FRAG` reader - The decimal part of the frequency divider factor."]
10pub type FRAG_R = crate::FieldReader;
11#[doc = "Field `FRAG` writer - The decimal part of the frequency divider factor."]
12pub type FRAG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13impl R {
14    #[doc = "Bits 0:11 - The integral part of the frequency divider factor."]
15    #[inline(always)]
16    pub fn clkdiv(&self) -> CLKDIV_R {
17        CLKDIV_R::new((self.bits & 0x0fff) as u16)
18    }
19    #[doc = "Bits 20:23 - The decimal part of the frequency divider factor."]
20    #[inline(always)]
21    pub fn frag(&self) -> FRAG_R {
22        FRAG_R::new(((self.bits >> 20) & 0x0f) as u8)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("CLKDIV")
29            .field("clkdiv", &self.clkdiv())
30            .field("frag", &self.frag())
31            .finish()
32    }
33}
34impl W {
35    #[doc = "Bits 0:11 - The integral part of the frequency divider factor."]
36    #[inline(always)]
37    pub fn clkdiv(&mut self) -> CLKDIV_W<CLKDIV_SPEC> {
38        CLKDIV_W::new(self, 0)
39    }
40    #[doc = "Bits 20:23 - The decimal part of the frequency divider factor."]
41    #[inline(always)]
42    pub fn frag(&mut self) -> FRAG_W<CLKDIV_SPEC> {
43        FRAG_W::new(self, 20)
44    }
45}
46#[doc = "Clock divider configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
47pub struct CLKDIV_SPEC;
48impl crate::RegisterSpec for CLKDIV_SPEC {
49    type Ux = u32;
50}
51#[doc = "`read()` method returns [`clkdiv::R`](R) reader structure"]
52impl crate::Readable for CLKDIV_SPEC {}
53#[doc = "`write(|w| ..)` method takes [`clkdiv::W`](W) writer structure"]
54impl crate::Writable for CLKDIV_SPEC {
55    type Safety = crate::Unsafe;
56    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
57    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
58}
59#[doc = "`reset()` method sets CLKDIV to value 0x02b6"]
60impl crate::Resettable for CLKDIV_SPEC {
61    const RESET_VALUE: u32 = 0x02b6;
62}
esp32c6/uart0/clkdiv.rs

esp32c6/uart0/
clkdiv.rs
