esp32c6/spi1/
timing_cali.rs

1#[doc = "Register `TIMING_CALI` reader"]
2pub type R = crate::R<TIMING_CALI_SPEC>;
3#[doc = "Register `TIMING_CALI` writer"]
4pub type W = crate::W<TIMING_CALI_SPEC>;
5#[doc = "Field `TIMING_CALI` reader - The bit is used to enable timing auto-calibration for all reading operations."]
6pub type TIMING_CALI_R = crate::BitReader;
7#[doc = "Field `TIMING_CALI` writer - The bit is used to enable timing auto-calibration for all reading operations."]
8pub type TIMING_CALI_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `EXTRA_DUMMY_CYCLELEN` reader - add extra dummy spi clock cycle length for spi clock calibration."]
10pub type EXTRA_DUMMY_CYCLELEN_R = crate::FieldReader;
11#[doc = "Field `EXTRA_DUMMY_CYCLELEN` writer - add extra dummy spi clock cycle length for spi clock calibration."]
12pub type EXTRA_DUMMY_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
13impl R {
14    #[doc = "Bit 1 - The bit is used to enable timing auto-calibration for all reading operations."]
15    #[inline(always)]
16    pub fn timing_cali(&self) -> TIMING_CALI_R {
17        TIMING_CALI_R::new(((self.bits >> 1) & 1) != 0)
18    }
19    #[doc = "Bits 2:4 - add extra dummy spi clock cycle length for spi clock calibration."]
20    #[inline(always)]
21    pub fn extra_dummy_cyclelen(&self) -> EXTRA_DUMMY_CYCLELEN_R {
22        EXTRA_DUMMY_CYCLELEN_R::new(((self.bits >> 2) & 7) as u8)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("TIMING_CALI")
29            .field("timing_cali", &self.timing_cali())
30            .field("extra_dummy_cyclelen", &self.extra_dummy_cyclelen())
31            .finish()
32    }
33}
34impl W {
35    #[doc = "Bit 1 - The bit is used to enable timing auto-calibration for all reading operations."]
36    #[inline(always)]
37    pub fn timing_cali(&mut self) -> TIMING_CALI_W<TIMING_CALI_SPEC> {
38        TIMING_CALI_W::new(self, 1)
39    }
40    #[doc = "Bits 2:4 - add extra dummy spi clock cycle length for spi clock calibration."]
41    #[inline(always)]
42    pub fn extra_dummy_cyclelen(&mut self) -> EXTRA_DUMMY_CYCLELEN_W<TIMING_CALI_SPEC> {
43        EXTRA_DUMMY_CYCLELEN_W::new(self, 2)
44    }
45}
46#[doc = "SPI1 timing control register\n\nYou can [`read`](crate::Reg::read) this register and get [`timing_cali::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timing_cali::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
47pub struct TIMING_CALI_SPEC;
48impl crate::RegisterSpec for TIMING_CALI_SPEC {
49    type Ux = u32;
50}
51#[doc = "`read()` method returns [`timing_cali::R`](R) reader structure"]
52impl crate::Readable for TIMING_CALI_SPEC {}
53#[doc = "`write(|w| ..)` method takes [`timing_cali::W`](W) writer structure"]
54impl crate::Writable for TIMING_CALI_SPEC {
55    type Safety = crate::Unsafe;
56    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
57    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
58}
59#[doc = "`reset()` method sets TIMING_CALI to value 0"]
60impl crate::Resettable for TIMING_CALI_SPEC {
61    const RESET_VALUE: u32 = 0;
62}
esp32c6/spi1/timing_cali.rs

esp32c6/spi1/
timing_cali.rs
