esp32c6/spi0/
sram_dwr_cmd.rs

1#[doc = "Register `SRAM_DWR_CMD` reader"]
2pub type R = crate::R<SRAM_DWR_CMD_SPEC>;
3#[doc = "Field `CACHE_SRAM_USR_WR_CMD_VALUE` reader - For SPI0,When cache mode is enable it is the write command value of command phase for sram."]
4pub type CACHE_SRAM_USR_WR_CMD_VALUE_R = crate::FieldReader<u16>;
5#[doc = "Field `CACHE_SRAM_USR_WR_CMD_BITLEN` reader - For SPI0,When cache mode is enable it is the in bits of command phase for sram. The register value shall be (bit_num-1)."]
6pub type CACHE_SRAM_USR_WR_CMD_BITLEN_R = crate::FieldReader;
7impl R {
8    #[doc = "Bits 0:15 - For SPI0,When cache mode is enable it is the write command value of command phase for sram."]
9    #[inline(always)]
10    pub fn cache_sram_usr_wr_cmd_value(&self) -> CACHE_SRAM_USR_WR_CMD_VALUE_R {
11        CACHE_SRAM_USR_WR_CMD_VALUE_R::new((self.bits & 0xffff) as u16)
12    }
13    #[doc = "Bits 28:31 - For SPI0,When cache mode is enable it is the in bits of command phase for sram. The register value shall be (bit_num-1)."]
14    #[inline(always)]
15    pub fn cache_sram_usr_wr_cmd_bitlen(&self) -> CACHE_SRAM_USR_WR_CMD_BITLEN_R {
16        CACHE_SRAM_USR_WR_CMD_BITLEN_R::new(((self.bits >> 28) & 0x0f) as u8)
17    }
18}
19#[cfg(feature = "impl-register-debug")]
20impl core::fmt::Debug for R {
21    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22        f.debug_struct("SRAM_DWR_CMD")
23            .field(
24                "cache_sram_usr_wr_cmd_value",
25                &self.cache_sram_usr_wr_cmd_value(),
26            )
27            .field(
28                "cache_sram_usr_wr_cmd_bitlen",
29                &self.cache_sram_usr_wr_cmd_bitlen(),
30            )
31            .finish()
32    }
33}
34#[doc = "SPI0 external RAM DDR write command control register\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_dwr_cmd::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
35pub struct SRAM_DWR_CMD_SPEC;
36impl crate::RegisterSpec for SRAM_DWR_CMD_SPEC {
37    type Ux = u32;
38}
39#[doc = "`read()` method returns [`sram_dwr_cmd::R`](R) reader structure"]
40impl crate::Readable for SRAM_DWR_CMD_SPEC {}
41#[doc = "`reset()` method sets SRAM_DWR_CMD to value 0"]
42impl crate::Resettable for SRAM_DWR_CMD_SPEC {
43    const RESET_VALUE: u32 = 0;
44}
esp32c6/spi0/sram_dwr_cmd.rs

esp32c6/spi0/
sram_dwr_cmd.rs
