esp32c6/spi0/
int_st.rs

1#[doc = "Register `INT_ST` reader"]
2pub type R = crate::R<INT_ST_SPEC>;
3#[doc = "Field `SLV_ST_END` reader - The status bit for SPI_MEM_SLV_ST_END_INT interrupt."]
4pub type SLV_ST_END_R = crate::BitReader;
5#[doc = "Field `MST_ST_END` reader - The status bit for SPI_MEM_MST_ST_END_INT interrupt."]
6pub type MST_ST_END_R = crate::BitReader;
7#[doc = "Field `ECC_ERR` reader - The status bit for SPI_MEM_ECC_ERR_INT interrupt."]
8pub type ECC_ERR_R = crate::BitReader;
9#[doc = "Field `PMS_REJECT` reader - The status bit for SPI_MEM_PMS_REJECT_INT interrupt."]
10pub type PMS_REJECT_R = crate::BitReader;
11#[doc = "Field `AXI_RADDR_ERR` reader - The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt."]
12pub type AXI_RADDR_ERR_R = crate::BitReader;
13#[doc = "Field `AXI_WR_FLASH_ERR` reader - The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt."]
14pub type AXI_WR_FLASH_ERR_R = crate::BitReader;
15#[doc = "Field `AXI_WADDR_ERR` reader - The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt."]
16pub type AXI_WADDR_ERR_R = crate::BitReader;
17impl R {
18    #[doc = "Bit 3 - The status bit for SPI_MEM_SLV_ST_END_INT interrupt."]
19    #[inline(always)]
20    pub fn slv_st_end(&self) -> SLV_ST_END_R {
21        SLV_ST_END_R::new(((self.bits >> 3) & 1) != 0)
22    }
23    #[doc = "Bit 4 - The status bit for SPI_MEM_MST_ST_END_INT interrupt."]
24    #[inline(always)]
25    pub fn mst_st_end(&self) -> MST_ST_END_R {
26        MST_ST_END_R::new(((self.bits >> 4) & 1) != 0)
27    }
28    #[doc = "Bit 5 - The status bit for SPI_MEM_ECC_ERR_INT interrupt."]
29    #[inline(always)]
30    pub fn ecc_err(&self) -> ECC_ERR_R {
31        ECC_ERR_R::new(((self.bits >> 5) & 1) != 0)
32    }
33    #[doc = "Bit 6 - The status bit for SPI_MEM_PMS_REJECT_INT interrupt."]
34    #[inline(always)]
35    pub fn pms_reject(&self) -> PMS_REJECT_R {
36        PMS_REJECT_R::new(((self.bits >> 6) & 1) != 0)
37    }
38    #[doc = "Bit 7 - The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt."]
39    #[inline(always)]
40    pub fn axi_raddr_err(&self) -> AXI_RADDR_ERR_R {
41        AXI_RADDR_ERR_R::new(((self.bits >> 7) & 1) != 0)
42    }
43    #[doc = "Bit 8 - The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt."]
44    #[inline(always)]
45    pub fn axi_wr_flash_err(&self) -> AXI_WR_FLASH_ERR_R {
46        AXI_WR_FLASH_ERR_R::new(((self.bits >> 8) & 1) != 0)
47    }
48    #[doc = "Bit 9 - The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt."]
49    #[inline(always)]
50    pub fn axi_waddr_err(&self) -> AXI_WADDR_ERR_R {
51        AXI_WADDR_ERR_R::new(((self.bits >> 9) & 1) != 0)
52    }
53}
54#[cfg(feature = "impl-register-debug")]
55impl core::fmt::Debug for R {
56    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
57        f.debug_struct("INT_ST")
58            .field("slv_st_end", &self.slv_st_end())
59            .field("mst_st_end", &self.mst_st_end())
60            .field("ecc_err", &self.ecc_err())
61            .field("pms_reject", &self.pms_reject())
62            .field("axi_raddr_err", &self.axi_raddr_err())
63            .field("axi_wr_flash_err", &self.axi_wr_flash_err())
64            .field("axi_waddr_err", &self.axi_waddr_err())
65            .finish()
66    }
67}
68#[doc = "SPI0 interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
69pub struct INT_ST_SPEC;
70impl crate::RegisterSpec for INT_ST_SPEC {
71    type Ux = u32;
72}
73#[doc = "`read()` method returns [`int_st::R`](R) reader structure"]
74impl crate::Readable for INT_ST_SPEC {}
75#[doc = "`reset()` method sets INT_ST to value 0"]
76impl crate::Resettable for INT_ST_SPEC {
77    const RESET_VALUE: u32 = 0;
78}
esp32c6/spi0/int_st.rs

esp32c6/spi0/
int_st.rs
