1#[doc = "Register `INT_RAW` reader"]
2pub type R = crate::R<INT_RAW_SPEC>;
3#[doc = "Register `INT_RAW` writer"]
4pub type W = crate::W<INT_RAW_SPEC>;
5#[doc = "Field `SLV_ST_END` reader - The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others"]
6pub type SLV_ST_END_R = crate::BitReader;
7#[doc = "Field `SLV_ST_END` writer - The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others"]
8pub type SLV_ST_END_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `MST_ST_END` reader - The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others."]
10pub type MST_ST_END_R = crate::BitReader;
11#[doc = "Field `MST_ST_END` writer - The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others."]
12pub type MST_ST_END_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `ECC_ERR` reader - The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered."]
14pub type ECC_ERR_R = crate::BitReader;
15#[doc = "Field `PMS_REJECT` reader - The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others."]
16pub type PMS_REJECT_R = crate::BitReader;
17#[doc = "Field `PMS_REJECT` writer - The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others."]
18pub type PMS_REJECT_W<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `AXI_RADDR_ERR` reader - The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others."]
20pub type AXI_RADDR_ERR_R = crate::BitReader;
21#[doc = "Field `AXI_RADDR_ERR` writer - The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others."]
22pub type AXI_RADDR_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
23#[doc = "Field `AXI_WR_FLASH_ERR` reader - The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others."]
24pub type AXI_WR_FLASH_ERR_R = crate::BitReader;
25#[doc = "Field `AXI_WADDR_ERR` reader - The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others."]
26pub type AXI_WADDR_ERR_R = crate::BitReader;
27impl R {
28 #[doc = "Bit 3 - The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others"]
29 #[inline(always)]
30 pub fn slv_st_end(&self) -> SLV_ST_END_R {
31 SLV_ST_END_R::new(((self.bits >> 3) & 1) != 0)
32 }
33 #[doc = "Bit 4 - The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others."]
34 #[inline(always)]
35 pub fn mst_st_end(&self) -> MST_ST_END_R {
36 MST_ST_END_R::new(((self.bits >> 4) & 1) != 0)
37 }
38 #[doc = "Bit 5 - The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered."]
39 #[inline(always)]
40 pub fn ecc_err(&self) -> ECC_ERR_R {
41 ECC_ERR_R::new(((self.bits >> 5) & 1) != 0)
42 }
43 #[doc = "Bit 6 - The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others."]
44 #[inline(always)]
45 pub fn pms_reject(&self) -> PMS_REJECT_R {
46 PMS_REJECT_R::new(((self.bits >> 6) & 1) != 0)
47 }
48 #[doc = "Bit 7 - The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others."]
49 #[inline(always)]
50 pub fn axi_raddr_err(&self) -> AXI_RADDR_ERR_R {
51 AXI_RADDR_ERR_R::new(((self.bits >> 7) & 1) != 0)
52 }
53 #[doc = "Bit 8 - The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others."]
54 #[inline(always)]
55 pub fn axi_wr_flash_err(&self) -> AXI_WR_FLASH_ERR_R {
56 AXI_WR_FLASH_ERR_R::new(((self.bits >> 8) & 1) != 0)
57 }
58 #[doc = "Bit 9 - The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others."]
59 #[inline(always)]
60 pub fn axi_waddr_err(&self) -> AXI_WADDR_ERR_R {
61 AXI_WADDR_ERR_R::new(((self.bits >> 9) & 1) != 0)
62 }
63}
64#[cfg(feature = "impl-register-debug")]
65impl core::fmt::Debug for R {
66 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
67 f.debug_struct("INT_RAW")
68 .field("slv_st_end", &self.slv_st_end())
69 .field("mst_st_end", &self.mst_st_end())
70 .field("ecc_err", &self.ecc_err())
71 .field("pms_reject", &self.pms_reject())
72 .field("axi_raddr_err", &self.axi_raddr_err())
73 .field("axi_wr_flash_err", &self.axi_wr_flash_err())
74 .field("axi_waddr_err", &self.axi_waddr_err())
75 .finish()
76 }
77}
78impl W {
79 #[doc = "Bit 3 - The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others"]
80 #[inline(always)]
81 pub fn slv_st_end(&mut self) -> SLV_ST_END_W<INT_RAW_SPEC> {
82 SLV_ST_END_W::new(self, 3)
83 }
84 #[doc = "Bit 4 - The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others."]
85 #[inline(always)]
86 pub fn mst_st_end(&mut self) -> MST_ST_END_W<INT_RAW_SPEC> {
87 MST_ST_END_W::new(self, 4)
88 }
89 #[doc = "Bit 6 - The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others."]
90 #[inline(always)]
91 pub fn pms_reject(&mut self) -> PMS_REJECT_W<INT_RAW_SPEC> {
92 PMS_REJECT_W::new(self, 6)
93 }
94 #[doc = "Bit 7 - The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others."]
95 #[inline(always)]
96 pub fn axi_raddr_err(&mut self) -> AXI_RADDR_ERR_W<INT_RAW_SPEC> {
97 AXI_RADDR_ERR_W::new(self, 7)
98 }
99}
100#[doc = "SPI0 interrupt raw register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
101pub struct INT_RAW_SPEC;
102impl crate::RegisterSpec for INT_RAW_SPEC {
103 type Ux = u32;
104}
105#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"]
106impl crate::Readable for INT_RAW_SPEC {}
107#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"]
108impl crate::Writable for INT_RAW_SPEC {
109 type Safety = crate::Unsafe;
110 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
111 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
112}
113#[doc = "`reset()` method sets INT_RAW to value 0"]
114impl crate::Resettable for INT_RAW_SPEC {
115 const RESET_VALUE: u32 = 0;
116}