esp32c6/pcnt/
int_ena.rs

1#[doc = "Register `INT_ENA` reader"]
2pub type R = crate::R<INT_ENA_SPEC>;
3#[doc = "Register `INT_ENA` writer"]
4pub type W = crate::W<INT_ENA_SPEC>;
5#[doc = "Field `CNT_THR_EVENT_U(0-3)` reader - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U%s_INT interrupt."]
6pub type CNT_THR_EVENT_U_R = crate::BitReader;
7#[doc = "Field `CNT_THR_EVENT_U(0-3)` writer - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U%s_INT interrupt."]
8pub type CNT_THR_EVENT_U_W<'a, REG> = crate::BitWriter<'a, REG>;
9impl R {
10    #[doc = "The interrupt enable bit for the PCNT_CNT_THR_EVENT_U(0-3)_INT interrupt."]
11    #[doc = ""]
12    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CNT_THR_EVENT_U0` field.</div>"]
13    #[inline(always)]
14    pub fn cnt_thr_event_u(&self, n: u8) -> CNT_THR_EVENT_U_R {
15        #[allow(clippy::no_effect)]
16        [(); 4][n as usize];
17        CNT_THR_EVENT_U_R::new(((self.bits >> n) & 1) != 0)
18    }
19    #[doc = "Iterator for array of:"]
20    #[doc = "The interrupt enable bit for the PCNT_CNT_THR_EVENT_U(0-3)_INT interrupt."]
21    #[inline(always)]
22    pub fn cnt_thr_event_u_iter(&self) -> impl Iterator<Item = CNT_THR_EVENT_U_R> + '_ {
23        (0..4).map(move |n| CNT_THR_EVENT_U_R::new(((self.bits >> n) & 1) != 0))
24    }
25    #[doc = "Bit 0 - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt."]
26    #[inline(always)]
27    pub fn cnt_thr_event_u0(&self) -> CNT_THR_EVENT_U_R {
28        CNT_THR_EVENT_U_R::new((self.bits & 1) != 0)
29    }
30    #[doc = "Bit 1 - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt."]
31    #[inline(always)]
32    pub fn cnt_thr_event_u1(&self) -> CNT_THR_EVENT_U_R {
33        CNT_THR_EVENT_U_R::new(((self.bits >> 1) & 1) != 0)
34    }
35    #[doc = "Bit 2 - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt."]
36    #[inline(always)]
37    pub fn cnt_thr_event_u2(&self) -> CNT_THR_EVENT_U_R {
38        CNT_THR_EVENT_U_R::new(((self.bits >> 2) & 1) != 0)
39    }
40    #[doc = "Bit 3 - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt."]
41    #[inline(always)]
42    pub fn cnt_thr_event_u3(&self) -> CNT_THR_EVENT_U_R {
43        CNT_THR_EVENT_U_R::new(((self.bits >> 3) & 1) != 0)
44    }
45}
46#[cfg(feature = "impl-register-debug")]
47impl core::fmt::Debug for R {
48    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
49        f.debug_struct("INT_ENA")
50            .field("cnt_thr_event_u0", &self.cnt_thr_event_u0())
51            .field("cnt_thr_event_u1", &self.cnt_thr_event_u1())
52            .field("cnt_thr_event_u2", &self.cnt_thr_event_u2())
53            .field("cnt_thr_event_u3", &self.cnt_thr_event_u3())
54            .finish()
55    }
56}
57impl W {
58    #[doc = "The interrupt enable bit for the PCNT_CNT_THR_EVENT_U(0-3)_INT interrupt."]
59    #[doc = ""]
60    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CNT_THR_EVENT_U0` field.</div>"]
61    #[inline(always)]
62    pub fn cnt_thr_event_u(&mut self, n: u8) -> CNT_THR_EVENT_U_W<INT_ENA_SPEC> {
63        #[allow(clippy::no_effect)]
64        [(); 4][n as usize];
65        CNT_THR_EVENT_U_W::new(self, n)
66    }
67    #[doc = "Bit 0 - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt."]
68    #[inline(always)]
69    pub fn cnt_thr_event_u0(&mut self) -> CNT_THR_EVENT_U_W<INT_ENA_SPEC> {
70        CNT_THR_EVENT_U_W::new(self, 0)
71    }
72    #[doc = "Bit 1 - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt."]
73    #[inline(always)]
74    pub fn cnt_thr_event_u1(&mut self) -> CNT_THR_EVENT_U_W<INT_ENA_SPEC> {
75        CNT_THR_EVENT_U_W::new(self, 1)
76    }
77    #[doc = "Bit 2 - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt."]
78    #[inline(always)]
79    pub fn cnt_thr_event_u2(&mut self) -> CNT_THR_EVENT_U_W<INT_ENA_SPEC> {
80        CNT_THR_EVENT_U_W::new(self, 2)
81    }
82    #[doc = "Bit 3 - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt."]
83    #[inline(always)]
84    pub fn cnt_thr_event_u3(&mut self) -> CNT_THR_EVENT_U_W<INT_ENA_SPEC> {
85        CNT_THR_EVENT_U_W::new(self, 3)
86    }
87}
88#[doc = "Interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
89pub struct INT_ENA_SPEC;
90impl crate::RegisterSpec for INT_ENA_SPEC {
91    type Ux = u32;
92}
93#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
94impl crate::Readable for INT_ENA_SPEC {}
95#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
96impl crate::Writable for INT_ENA_SPEC {
97    type Safety = crate::Unsafe;
98    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
99    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
100}
101#[doc = "`reset()` method sets INT_ENA to value 0"]
102impl crate::Resettable for INT_ENA_SPEC {
103    const RESET_VALUE: u32 = 0;
104}
esp32c6/pcnt/int_ena.rs

esp32c6/pcnt/
int_ena.rs
