esp32c6/modem_lpcon/
clk_conf_force_on.rs

1#[doc = "Register `CLK_CONF_FORCE_ON` reader"]
2pub type R = crate::R<CLK_CONF_FORCE_ON_SPEC>;
3#[doc = "Register `CLK_CONF_FORCE_ON` writer"]
4pub type W = crate::W<CLK_CONF_FORCE_ON_SPEC>;
5#[doc = "Field `CLK_WIFIPWR_FO` reader - "]
6pub type CLK_WIFIPWR_FO_R = crate::BitReader;
7#[doc = "Field `CLK_WIFIPWR_FO` writer - "]
8pub type CLK_WIFIPWR_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CLK_COEX_FO` reader - "]
10pub type CLK_COEX_FO_R = crate::BitReader;
11#[doc = "Field `CLK_COEX_FO` writer - "]
12pub type CLK_COEX_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CLK_I2C_MST_FO` reader - "]
14pub type CLK_I2C_MST_FO_R = crate::BitReader;
15#[doc = "Field `CLK_I2C_MST_FO` writer - "]
16pub type CLK_I2C_MST_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CLK_LP_TIMER_FO` reader - "]
18pub type CLK_LP_TIMER_FO_R = crate::BitReader;
19#[doc = "Field `CLK_LP_TIMER_FO` writer - "]
20pub type CLK_LP_TIMER_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CLK_BCMEM_FO` reader - "]
22pub type CLK_BCMEM_FO_R = crate::BitReader;
23#[doc = "Field `CLK_BCMEM_FO` writer - "]
24pub type CLK_BCMEM_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `CLK_I2C_MST_MEM_FO` reader - "]
26pub type CLK_I2C_MST_MEM_FO_R = crate::BitReader;
27#[doc = "Field `CLK_I2C_MST_MEM_FO` writer - "]
28pub type CLK_I2C_MST_MEM_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `CLK_CHAN_FREQ_MEM_FO` reader - "]
30pub type CLK_CHAN_FREQ_MEM_FO_R = crate::BitReader;
31#[doc = "Field `CLK_CHAN_FREQ_MEM_FO` writer - "]
32pub type CLK_CHAN_FREQ_MEM_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `CLK_PBUS_MEM_FO` reader - "]
34pub type CLK_PBUS_MEM_FO_R = crate::BitReader;
35#[doc = "Field `CLK_PBUS_MEM_FO` writer - "]
36pub type CLK_PBUS_MEM_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `CLK_AGC_MEM_FO` reader - "]
38pub type CLK_AGC_MEM_FO_R = crate::BitReader;
39#[doc = "Field `CLK_AGC_MEM_FO` writer - "]
40pub type CLK_AGC_MEM_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `CLK_DC_MEM_FO` reader - "]
42pub type CLK_DC_MEM_FO_R = crate::BitReader;
43#[doc = "Field `CLK_DC_MEM_FO` writer - "]
44pub type CLK_DC_MEM_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
45impl R {
46    #[doc = "Bit 0"]
47    #[inline(always)]
48    pub fn clk_wifipwr_fo(&self) -> CLK_WIFIPWR_FO_R {
49        CLK_WIFIPWR_FO_R::new((self.bits & 1) != 0)
50    }
51    #[doc = "Bit 1"]
52    #[inline(always)]
53    pub fn clk_coex_fo(&self) -> CLK_COEX_FO_R {
54        CLK_COEX_FO_R::new(((self.bits >> 1) & 1) != 0)
55    }
56    #[doc = "Bit 2"]
57    #[inline(always)]
58    pub fn clk_i2c_mst_fo(&self) -> CLK_I2C_MST_FO_R {
59        CLK_I2C_MST_FO_R::new(((self.bits >> 2) & 1) != 0)
60    }
61    #[doc = "Bit 3"]
62    #[inline(always)]
63    pub fn clk_lp_timer_fo(&self) -> CLK_LP_TIMER_FO_R {
64        CLK_LP_TIMER_FO_R::new(((self.bits >> 3) & 1) != 0)
65    }
66    #[doc = "Bit 4"]
67    #[inline(always)]
68    pub fn clk_bcmem_fo(&self) -> CLK_BCMEM_FO_R {
69        CLK_BCMEM_FO_R::new(((self.bits >> 4) & 1) != 0)
70    }
71    #[doc = "Bit 5"]
72    #[inline(always)]
73    pub fn clk_i2c_mst_mem_fo(&self) -> CLK_I2C_MST_MEM_FO_R {
74        CLK_I2C_MST_MEM_FO_R::new(((self.bits >> 5) & 1) != 0)
75    }
76    #[doc = "Bit 6"]
77    #[inline(always)]
78    pub fn clk_chan_freq_mem_fo(&self) -> CLK_CHAN_FREQ_MEM_FO_R {
79        CLK_CHAN_FREQ_MEM_FO_R::new(((self.bits >> 6) & 1) != 0)
80    }
81    #[doc = "Bit 7"]
82    #[inline(always)]
83    pub fn clk_pbus_mem_fo(&self) -> CLK_PBUS_MEM_FO_R {
84        CLK_PBUS_MEM_FO_R::new(((self.bits >> 7) & 1) != 0)
85    }
86    #[doc = "Bit 8"]
87    #[inline(always)]
88    pub fn clk_agc_mem_fo(&self) -> CLK_AGC_MEM_FO_R {
89        CLK_AGC_MEM_FO_R::new(((self.bits >> 8) & 1) != 0)
90    }
91    #[doc = "Bit 9"]
92    #[inline(always)]
93    pub fn clk_dc_mem_fo(&self) -> CLK_DC_MEM_FO_R {
94        CLK_DC_MEM_FO_R::new(((self.bits >> 9) & 1) != 0)
95    }
96}
97#[cfg(feature = "impl-register-debug")]
98impl core::fmt::Debug for R {
99    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
100        f.debug_struct("CLK_CONF_FORCE_ON")
101            .field("clk_wifipwr_fo", &self.clk_wifipwr_fo())
102            .field("clk_coex_fo", &self.clk_coex_fo())
103            .field("clk_i2c_mst_fo", &self.clk_i2c_mst_fo())
104            .field("clk_lp_timer_fo", &self.clk_lp_timer_fo())
105            .field("clk_bcmem_fo", &self.clk_bcmem_fo())
106            .field("clk_i2c_mst_mem_fo", &self.clk_i2c_mst_mem_fo())
107            .field("clk_chan_freq_mem_fo", &self.clk_chan_freq_mem_fo())
108            .field("clk_pbus_mem_fo", &self.clk_pbus_mem_fo())
109            .field("clk_agc_mem_fo", &self.clk_agc_mem_fo())
110            .field("clk_dc_mem_fo", &self.clk_dc_mem_fo())
111            .finish()
112    }
113}
114impl W {
115    #[doc = "Bit 0"]
116    #[inline(always)]
117    pub fn clk_wifipwr_fo(&mut self) -> CLK_WIFIPWR_FO_W<CLK_CONF_FORCE_ON_SPEC> {
118        CLK_WIFIPWR_FO_W::new(self, 0)
119    }
120    #[doc = "Bit 1"]
121    #[inline(always)]
122    pub fn clk_coex_fo(&mut self) -> CLK_COEX_FO_W<CLK_CONF_FORCE_ON_SPEC> {
123        CLK_COEX_FO_W::new(self, 1)
124    }
125    #[doc = "Bit 2"]
126    #[inline(always)]
127    pub fn clk_i2c_mst_fo(&mut self) -> CLK_I2C_MST_FO_W<CLK_CONF_FORCE_ON_SPEC> {
128        CLK_I2C_MST_FO_W::new(self, 2)
129    }
130    #[doc = "Bit 3"]
131    #[inline(always)]
132    pub fn clk_lp_timer_fo(&mut self) -> CLK_LP_TIMER_FO_W<CLK_CONF_FORCE_ON_SPEC> {
133        CLK_LP_TIMER_FO_W::new(self, 3)
134    }
135    #[doc = "Bit 4"]
136    #[inline(always)]
137    pub fn clk_bcmem_fo(&mut self) -> CLK_BCMEM_FO_W<CLK_CONF_FORCE_ON_SPEC> {
138        CLK_BCMEM_FO_W::new(self, 4)
139    }
140    #[doc = "Bit 5"]
141    #[inline(always)]
142    pub fn clk_i2c_mst_mem_fo(&mut self) -> CLK_I2C_MST_MEM_FO_W<CLK_CONF_FORCE_ON_SPEC> {
143        CLK_I2C_MST_MEM_FO_W::new(self, 5)
144    }
145    #[doc = "Bit 6"]
146    #[inline(always)]
147    pub fn clk_chan_freq_mem_fo(&mut self) -> CLK_CHAN_FREQ_MEM_FO_W<CLK_CONF_FORCE_ON_SPEC> {
148        CLK_CHAN_FREQ_MEM_FO_W::new(self, 6)
149    }
150    #[doc = "Bit 7"]
151    #[inline(always)]
152    pub fn clk_pbus_mem_fo(&mut self) -> CLK_PBUS_MEM_FO_W<CLK_CONF_FORCE_ON_SPEC> {
153        CLK_PBUS_MEM_FO_W::new(self, 7)
154    }
155    #[doc = "Bit 8"]
156    #[inline(always)]
157    pub fn clk_agc_mem_fo(&mut self) -> CLK_AGC_MEM_FO_W<CLK_CONF_FORCE_ON_SPEC> {
158        CLK_AGC_MEM_FO_W::new(self, 8)
159    }
160    #[doc = "Bit 9"]
161    #[inline(always)]
162    pub fn clk_dc_mem_fo(&mut self) -> CLK_DC_MEM_FO_W<CLK_CONF_FORCE_ON_SPEC> {
163        CLK_DC_MEM_FO_W::new(self, 9)
164    }
165}
166#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_conf_force_on::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_conf_force_on::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
167pub struct CLK_CONF_FORCE_ON_SPEC;
168impl crate::RegisterSpec for CLK_CONF_FORCE_ON_SPEC {
169    type Ux = u32;
170}
171#[doc = "`read()` method returns [`clk_conf_force_on::R`](R) reader structure"]
172impl crate::Readable for CLK_CONF_FORCE_ON_SPEC {}
173#[doc = "`write(|w| ..)` method takes [`clk_conf_force_on::W`](W) writer structure"]
174impl crate::Writable for CLK_CONF_FORCE_ON_SPEC {
175    type Safety = crate::Unsafe;
176    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
177    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
178}
179#[doc = "`reset()` method sets CLK_CONF_FORCE_ON to value 0"]
180impl crate::Resettable for CLK_CONF_FORCE_ON_SPEC {
181    const RESET_VALUE: u32 = 0;
182}
esp32c6/modem_lpcon/clk_conf_force_on.rs

esp32c6/modem_lpcon/
clk_conf_force_on.rs
