esp32c6/lp_uart/
clk_conf.rs

1#[doc = "Register `CLK_CONF` reader"]
2pub type R = crate::R<CLK_CONF_SPEC>;
3#[doc = "Register `CLK_CONF` writer"]
4pub type W = crate::W<CLK_CONF_SPEC>;
5#[doc = "Field `SCLK_DIV_B` reader - The denominator of the frequency divider factor."]
6pub type SCLK_DIV_B_R = crate::FieldReader;
7#[doc = "Field `SCLK_DIV_B` writer - The denominator of the frequency divider factor."]
8pub type SCLK_DIV_B_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
9#[doc = "Field `SCLK_DIV_A` reader - The numerator of the frequency divider factor."]
10pub type SCLK_DIV_A_R = crate::FieldReader;
11#[doc = "Field `SCLK_DIV_A` writer - The numerator of the frequency divider factor."]
12pub type SCLK_DIV_A_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
13#[doc = "Field `SCLK_DIV_NUM` reader - The integral part of the frequency divider factor."]
14pub type SCLK_DIV_NUM_R = crate::FieldReader;
15#[doc = "Field `SCLK_DIV_NUM` writer - The integral part of the frequency divider factor."]
16pub type SCLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
17#[doc = "Field `SCLK_SEL` reader - UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL."]
18pub type SCLK_SEL_R = crate::FieldReader;
19#[doc = "Field `SCLK_SEL` writer - UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL."]
20pub type SCLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21#[doc = "Field `SCLK_EN` reader - Set this bit to enable UART Tx/Rx clock."]
22pub type SCLK_EN_R = crate::BitReader;
23#[doc = "Field `SCLK_EN` writer - Set this bit to enable UART Tx/Rx clock."]
24pub type SCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `RST_CORE` reader - Write 1 then write 0 to this bit to reset UART Tx/Rx."]
26pub type RST_CORE_R = crate::BitReader;
27#[doc = "Field `RST_CORE` writer - Write 1 then write 0 to this bit to reset UART Tx/Rx."]
28pub type RST_CORE_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `TX_SCLK_EN` reader - Set this bit to enable UART Tx clock."]
30pub type TX_SCLK_EN_R = crate::BitReader;
31#[doc = "Field `TX_SCLK_EN` writer - Set this bit to enable UART Tx clock."]
32pub type TX_SCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `RX_SCLK_EN` reader - Set this bit to enable UART Rx clock."]
34pub type RX_SCLK_EN_R = crate::BitReader;
35#[doc = "Field `RX_SCLK_EN` writer - Set this bit to enable UART Rx clock."]
36pub type RX_SCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `TX_RST_CORE` reader - Write 1 then write 0 to this bit to reset UART Tx."]
38pub type TX_RST_CORE_R = crate::BitReader;
39#[doc = "Field `TX_RST_CORE` writer - Write 1 then write 0 to this bit to reset UART Tx."]
40pub type TX_RST_CORE_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `RX_RST_CORE` reader - Write 1 then write 0 to this bit to reset UART Rx."]
42pub type RX_RST_CORE_R = crate::BitReader;
43#[doc = "Field `RX_RST_CORE` writer - Write 1 then write 0 to this bit to reset UART Rx."]
44pub type RX_RST_CORE_W<'a, REG> = crate::BitWriter<'a, REG>;
45impl R {
46    #[doc = "Bits 0:5 - The denominator of the frequency divider factor."]
47    #[inline(always)]
48    pub fn sclk_div_b(&self) -> SCLK_DIV_B_R {
49        SCLK_DIV_B_R::new((self.bits & 0x3f) as u8)
50    }
51    #[doc = "Bits 6:11 - The numerator of the frequency divider factor."]
52    #[inline(always)]
53    pub fn sclk_div_a(&self) -> SCLK_DIV_A_R {
54        SCLK_DIV_A_R::new(((self.bits >> 6) & 0x3f) as u8)
55    }
56    #[doc = "Bits 12:19 - The integral part of the frequency divider factor."]
57    #[inline(always)]
58    pub fn sclk_div_num(&self) -> SCLK_DIV_NUM_R {
59        SCLK_DIV_NUM_R::new(((self.bits >> 12) & 0xff) as u8)
60    }
61    #[doc = "Bits 20:21 - UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL."]
62    #[inline(always)]
63    pub fn sclk_sel(&self) -> SCLK_SEL_R {
64        SCLK_SEL_R::new(((self.bits >> 20) & 3) as u8)
65    }
66    #[doc = "Bit 22 - Set this bit to enable UART Tx/Rx clock."]
67    #[inline(always)]
68    pub fn sclk_en(&self) -> SCLK_EN_R {
69        SCLK_EN_R::new(((self.bits >> 22) & 1) != 0)
70    }
71    #[doc = "Bit 23 - Write 1 then write 0 to this bit to reset UART Tx/Rx."]
72    #[inline(always)]
73    pub fn rst_core(&self) -> RST_CORE_R {
74        RST_CORE_R::new(((self.bits >> 23) & 1) != 0)
75    }
76    #[doc = "Bit 24 - Set this bit to enable UART Tx clock."]
77    #[inline(always)]
78    pub fn tx_sclk_en(&self) -> TX_SCLK_EN_R {
79        TX_SCLK_EN_R::new(((self.bits >> 24) & 1) != 0)
80    }
81    #[doc = "Bit 25 - Set this bit to enable UART Rx clock."]
82    #[inline(always)]
83    pub fn rx_sclk_en(&self) -> RX_SCLK_EN_R {
84        RX_SCLK_EN_R::new(((self.bits >> 25) & 1) != 0)
85    }
86    #[doc = "Bit 26 - Write 1 then write 0 to this bit to reset UART Tx."]
87    #[inline(always)]
88    pub fn tx_rst_core(&self) -> TX_RST_CORE_R {
89        TX_RST_CORE_R::new(((self.bits >> 26) & 1) != 0)
90    }
91    #[doc = "Bit 27 - Write 1 then write 0 to this bit to reset UART Rx."]
92    #[inline(always)]
93    pub fn rx_rst_core(&self) -> RX_RST_CORE_R {
94        RX_RST_CORE_R::new(((self.bits >> 27) & 1) != 0)
95    }
96}
97#[cfg(feature = "impl-register-debug")]
98impl core::fmt::Debug for R {
99    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
100        f.debug_struct("CLK_CONF")
101            .field("sclk_div_b", &self.sclk_div_b())
102            .field("sclk_div_a", &self.sclk_div_a())
103            .field("sclk_div_num", &self.sclk_div_num())
104            .field("sclk_sel", &self.sclk_sel())
105            .field("sclk_en", &self.sclk_en())
106            .field("rst_core", &self.rst_core())
107            .field("tx_sclk_en", &self.tx_sclk_en())
108            .field("rx_sclk_en", &self.rx_sclk_en())
109            .field("tx_rst_core", &self.tx_rst_core())
110            .field("rx_rst_core", &self.rx_rst_core())
111            .finish()
112    }
113}
114impl W {
115    #[doc = "Bits 0:5 - The denominator of the frequency divider factor."]
116    #[inline(always)]
117    pub fn sclk_div_b(&mut self) -> SCLK_DIV_B_W<CLK_CONF_SPEC> {
118        SCLK_DIV_B_W::new(self, 0)
119    }
120    #[doc = "Bits 6:11 - The numerator of the frequency divider factor."]
121    #[inline(always)]
122    pub fn sclk_div_a(&mut self) -> SCLK_DIV_A_W<CLK_CONF_SPEC> {
123        SCLK_DIV_A_W::new(self, 6)
124    }
125    #[doc = "Bits 12:19 - The integral part of the frequency divider factor."]
126    #[inline(always)]
127    pub fn sclk_div_num(&mut self) -> SCLK_DIV_NUM_W<CLK_CONF_SPEC> {
128        SCLK_DIV_NUM_W::new(self, 12)
129    }
130    #[doc = "Bits 20:21 - UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL."]
131    #[inline(always)]
132    pub fn sclk_sel(&mut self) -> SCLK_SEL_W<CLK_CONF_SPEC> {
133        SCLK_SEL_W::new(self, 20)
134    }
135    #[doc = "Bit 22 - Set this bit to enable UART Tx/Rx clock."]
136    #[inline(always)]
137    pub fn sclk_en(&mut self) -> SCLK_EN_W<CLK_CONF_SPEC> {
138        SCLK_EN_W::new(self, 22)
139    }
140    #[doc = "Bit 23 - Write 1 then write 0 to this bit to reset UART Tx/Rx."]
141    #[inline(always)]
142    pub fn rst_core(&mut self) -> RST_CORE_W<CLK_CONF_SPEC> {
143        RST_CORE_W::new(self, 23)
144    }
145    #[doc = "Bit 24 - Set this bit to enable UART Tx clock."]
146    #[inline(always)]
147    pub fn tx_sclk_en(&mut self) -> TX_SCLK_EN_W<CLK_CONF_SPEC> {
148        TX_SCLK_EN_W::new(self, 24)
149    }
150    #[doc = "Bit 25 - Set this bit to enable UART Rx clock."]
151    #[inline(always)]
152    pub fn rx_sclk_en(&mut self) -> RX_SCLK_EN_W<CLK_CONF_SPEC> {
153        RX_SCLK_EN_W::new(self, 25)
154    }
155    #[doc = "Bit 26 - Write 1 then write 0 to this bit to reset UART Tx."]
156    #[inline(always)]
157    pub fn tx_rst_core(&mut self) -> TX_RST_CORE_W<CLK_CONF_SPEC> {
158        TX_RST_CORE_W::new(self, 26)
159    }
160    #[doc = "Bit 27 - Write 1 then write 0 to this bit to reset UART Rx."]
161    #[inline(always)]
162    pub fn rx_rst_core(&mut self) -> RX_RST_CORE_W<CLK_CONF_SPEC> {
163        RX_RST_CORE_W::new(self, 27)
164    }
165}
166#[doc = "UART core clock configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
167pub struct CLK_CONF_SPEC;
168impl crate::RegisterSpec for CLK_CONF_SPEC {
169    type Ux = u32;
170}
171#[doc = "`read()` method returns [`clk_conf::R`](R) reader structure"]
172impl crate::Readable for CLK_CONF_SPEC {}
173#[doc = "`write(|w| ..)` method takes [`clk_conf::W`](W) writer structure"]
174impl crate::Writable for CLK_CONF_SPEC {
175    type Safety = crate::Unsafe;
176    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
177    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
178}
179#[doc = "`reset()` method sets CLK_CONF to value 0x0370_1000"]
180impl crate::Resettable for CLK_CONF_SPEC {
181    const RESET_VALUE: u32 = 0x0370_1000;
182}
esp32c6/lp_uart/clk_conf.rs

esp32c6/lp_uart/
clk_conf.rs
