esp32c6/i2c_ana_mst/
ana_conf2.rs1#[doc = "Register `ANA_CONF2` reader"]
2pub type R = crate::R<ANA_CONF2_SPEC>;
3#[doc = "Register `ANA_CONF2` writer"]
4pub type W = crate::W<ANA_CONF2_SPEC>;
5#[doc = "Field `BIAS_MST_SEL` reader - Configures which I2C master the following analog modules uses. If the corresponding bit is set to 1, I2C0 master is used for communication; if set to 0, I2C1 master is used."]
6pub type BIAS_MST_SEL_R = crate::BitReader;
7#[doc = "Field `BIAS_MST_SEL` writer - Configures which I2C master the following analog modules uses. If the corresponding bit is set to 1, I2C0 master is used for communication; if set to 0, I2C1 master is used."]
8pub type BIAS_MST_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `BBPLL_MST_SEL` reader - Configures which I2C master the following analog modules uses. If the corresponding bit is set to 1, I2C0 master is used for communication; if set to 0, I2C1 master is used."]
10pub type BBPLL_MST_SEL_R = crate::BitReader;
11#[doc = "Field `BBPLL_MST_SEL` writer - Configures which I2C master the following analog modules uses. If the corresponding bit is set to 1, I2C0 master is used for communication; if set to 0, I2C1 master is used."]
12pub type BBPLL_MST_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `ULP_CAL_MST_SEL` reader - Configures which I2C master the following analog modules uses. If the corresponding bit is set to 1, I2C0 master is used for communication; if set to 0, I2C1 master is used."]
14pub type ULP_CAL_MST_SEL_R = crate::BitReader;
15#[doc = "Field `ULP_CAL_MST_SEL` writer - Configures which I2C master the following analog modules uses. If the corresponding bit is set to 1, I2C0 master is used for communication; if set to 0, I2C1 master is used."]
16pub type ULP_CAL_MST_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SAR_I2C_MST_SEL` reader - Configures which I2C master the following analog modules uses. If the corresponding bit is set to 1, I2C0 master is used for communication; if set to 0, I2C1 master is used."]
18pub type SAR_I2C_MST_SEL_R = crate::BitReader;
19#[doc = "Field `SAR_I2C_MST_SEL` writer - Configures which I2C master the following analog modules uses. If the corresponding bit is set to 1, I2C0 master is used for communication; if set to 0, I2C1 master is used."]
20pub type SAR_I2C_MST_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `DIG_REG_MST_SEL` reader - Configures which I2C master the following analog modules uses. If the corresponding bit is set to 1, I2C0 master is used for communication; if set to 0, I2C1 master is used."]
22pub type DIG_REG_MST_SEL_R = crate::BitReader;
23#[doc = "Field `DIG_REG_MST_SEL` writer - Configures which I2C master the following analog modules uses. If the corresponding bit is set to 1, I2C0 master is used for communication; if set to 0, I2C1 master is used."]
24pub type DIG_REG_MST_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `SAR_FORCE_PU` reader - ?"]
26pub type SAR_FORCE_PU_R = crate::BitReader;
27#[doc = "Field `SAR_FORCE_PU` writer - ?"]
28pub type SAR_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `BBPLL_M` reader - Clear to enable BBPLL"]
30pub type BBPLL_M_R = crate::BitReader;
31#[doc = "Field `BBPLL_M` writer - Clear to enable BBPLL"]
32pub type BBPLL_M_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `SAR_FORCE_PD` reader - ?"]
34pub type SAR_FORCE_PD_R = crate::BitReader;
35#[doc = "Field `SAR_FORCE_PD` writer - ?"]
36pub type SAR_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `STATUS` reader - ?"]
38pub type STATUS_R = crate::FieldReader;
39impl R {
40 #[doc = "Bit 8 - Configures which I2C master the following analog modules uses. If the corresponding bit is set to 1, I2C0 master is used for communication; if set to 0, I2C1 master is used."]
41 #[inline(always)]
42 pub fn bias_mst_sel(&self) -> BIAS_MST_SEL_R {
43 BIAS_MST_SEL_R::new(((self.bits >> 8) & 1) != 0)
44 }
45 #[doc = "Bit 9 - Configures which I2C master the following analog modules uses. If the corresponding bit is set to 1, I2C0 master is used for communication; if set to 0, I2C1 master is used."]
46 #[inline(always)]
47 pub fn bbpll_mst_sel(&self) -> BBPLL_MST_SEL_R {
48 BBPLL_MST_SEL_R::new(((self.bits >> 9) & 1) != 0)
49 }
50 #[doc = "Bit 10 - Configures which I2C master the following analog modules uses. If the corresponding bit is set to 1, I2C0 master is used for communication; if set to 0, I2C1 master is used."]
51 #[inline(always)]
52 pub fn ulp_cal_mst_sel(&self) -> ULP_CAL_MST_SEL_R {
53 ULP_CAL_MST_SEL_R::new(((self.bits >> 10) & 1) != 0)
54 }
55 #[doc = "Bit 11 - Configures which I2C master the following analog modules uses. If the corresponding bit is set to 1, I2C0 master is used for communication; if set to 0, I2C1 master is used."]
56 #[inline(always)]
57 pub fn sar_i2c_mst_sel(&self) -> SAR_I2C_MST_SEL_R {
58 SAR_I2C_MST_SEL_R::new(((self.bits >> 11) & 1) != 0)
59 }
60 #[doc = "Bit 12 - Configures which I2C master the following analog modules uses. If the corresponding bit is set to 1, I2C0 master is used for communication; if set to 0, I2C1 master is used."]
61 #[inline(always)]
62 pub fn dig_reg_mst_sel(&self) -> DIG_REG_MST_SEL_R {
63 DIG_REG_MST_SEL_R::new(((self.bits >> 12) & 1) != 0)
64 }
65 #[doc = "Bit 16 - ?"]
66 #[inline(always)]
67 pub fn sar_force_pu(&self) -> SAR_FORCE_PU_R {
68 SAR_FORCE_PU_R::new(((self.bits >> 16) & 1) != 0)
69 }
70 #[doc = "Bit 17 - Clear to enable BBPLL"]
71 #[inline(always)]
72 pub fn bbpll_m(&self) -> BBPLL_M_R {
73 BBPLL_M_R::new(((self.bits >> 17) & 1) != 0)
74 }
75 #[doc = "Bit 18 - ?"]
76 #[inline(always)]
77 pub fn sar_force_pd(&self) -> SAR_FORCE_PD_R {
78 SAR_FORCE_PD_R::new(((self.bits >> 18) & 1) != 0)
79 }
80 #[doc = "Bits 24:31 - ?"]
81 #[inline(always)]
82 pub fn status(&self) -> STATUS_R {
83 STATUS_R::new(((self.bits >> 24) & 0xff) as u8)
84 }
85}
86#[cfg(feature = "impl-register-debug")]
87impl core::fmt::Debug for R {
88 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
89 f.debug_struct("ANA_CONF2")
90 .field("bias_mst_sel", &self.bias_mst_sel())
91 .field("bbpll_mst_sel", &self.bbpll_mst_sel())
92 .field("ulp_cal_mst_sel", &self.ulp_cal_mst_sel())
93 .field("sar_i2c_mst_sel", &self.sar_i2c_mst_sel())
94 .field("dig_reg_mst_sel", &self.dig_reg_mst_sel())
95 .field("sar_force_pd", &self.sar_force_pd())
96 .field("bbpll_m", &self.bbpll_m())
97 .field("sar_force_pu", &self.sar_force_pu())
98 .field("status", &self.status())
99 .finish()
100 }
101}
102impl W {
103 #[doc = "Bit 8 - Configures which I2C master the following analog modules uses. If the corresponding bit is set to 1, I2C0 master is used for communication; if set to 0, I2C1 master is used."]
104 #[inline(always)]
105 pub fn bias_mst_sel(&mut self) -> BIAS_MST_SEL_W<ANA_CONF2_SPEC> {
106 BIAS_MST_SEL_W::new(self, 8)
107 }
108 #[doc = "Bit 9 - Configures which I2C master the following analog modules uses. If the corresponding bit is set to 1, I2C0 master is used for communication; if set to 0, I2C1 master is used."]
109 #[inline(always)]
110 pub fn bbpll_mst_sel(&mut self) -> BBPLL_MST_SEL_W<ANA_CONF2_SPEC> {
111 BBPLL_MST_SEL_W::new(self, 9)
112 }
113 #[doc = "Bit 10 - Configures which I2C master the following analog modules uses. If the corresponding bit is set to 1, I2C0 master is used for communication; if set to 0, I2C1 master is used."]
114 #[inline(always)]
115 pub fn ulp_cal_mst_sel(&mut self) -> ULP_CAL_MST_SEL_W<ANA_CONF2_SPEC> {
116 ULP_CAL_MST_SEL_W::new(self, 10)
117 }
118 #[doc = "Bit 11 - Configures which I2C master the following analog modules uses. If the corresponding bit is set to 1, I2C0 master is used for communication; if set to 0, I2C1 master is used."]
119 #[inline(always)]
120 pub fn sar_i2c_mst_sel(&mut self) -> SAR_I2C_MST_SEL_W<ANA_CONF2_SPEC> {
121 SAR_I2C_MST_SEL_W::new(self, 11)
122 }
123 #[doc = "Bit 12 - Configures which I2C master the following analog modules uses. If the corresponding bit is set to 1, I2C0 master is used for communication; if set to 0, I2C1 master is used."]
124 #[inline(always)]
125 pub fn dig_reg_mst_sel(&mut self) -> DIG_REG_MST_SEL_W<ANA_CONF2_SPEC> {
126 DIG_REG_MST_SEL_W::new(self, 12)
127 }
128 #[doc = "Bit 16 - ?"]
129 #[inline(always)]
130 pub fn sar_force_pu(&mut self) -> SAR_FORCE_PU_W<ANA_CONF2_SPEC> {
131 SAR_FORCE_PU_W::new(self, 16)
132 }
133 #[doc = "Bit 17 - Clear to enable BBPLL"]
134 #[inline(always)]
135 pub fn bbpll_m(&mut self) -> BBPLL_M_W<ANA_CONF2_SPEC> {
136 BBPLL_M_W::new(self, 17)
137 }
138 #[doc = "Bit 18 - ?"]
139 #[inline(always)]
140 pub fn sar_force_pd(&mut self) -> SAR_FORCE_PD_W<ANA_CONF2_SPEC> {
141 SAR_FORCE_PD_W::new(self, 18)
142 }
143}
144#[doc = "ANA_CONF2 register\n\nYou can [`read`](crate::Reg::read) this register and get [`ana_conf2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ana_conf2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
145pub struct ANA_CONF2_SPEC;
146impl crate::RegisterSpec for ANA_CONF2_SPEC {
147 type Ux = u32;
148}
149#[doc = "`read()` method returns [`ana_conf2::R`](R) reader structure"]
150impl crate::Readable for ANA_CONF2_SPEC {}
151#[doc = "`write(|w| ..)` method takes [`ana_conf2::W`](W) writer structure"]
152impl crate::Writable for ANA_CONF2_SPEC {
153 type Safety = crate::Unsafe;
154 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
155 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
156}
157#[doc = "`reset()` method sets ANA_CONF2 to value 0"]
158impl crate::Resettable for ANA_CONF2_SPEC {
159 const RESET_VALUE: u32 = 0;
160}