1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `RXFIFO_WM` writer - Set this bit to clear I2C_RXFIFO_WM_INT interrupt."]
4pub type RXFIFO_WM_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `TXFIFO_WM` writer - Set this bit to clear I2C_TXFIFO_WM_INT interrupt."]
6pub type TXFIFO_WM_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `RXFIFO_OVF` writer - Set this bit to clear I2C_RXFIFO_OVF_INT interrupt."]
8pub type RXFIFO_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `END_DETECT` writer - Set this bit to clear the I2C_END_DETECT_INT interrupt."]
10pub type END_DETECT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
11#[doc = "Field `BYTE_TRANS_DONE` writer - Set this bit to clear the I2C_END_DETECT_INT interrupt."]
12pub type BYTE_TRANS_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `ARBITRATION_LOST` writer - Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt."]
14pub type ARBITRATION_LOST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
15#[doc = "Field `MST_TXFIFO_UDF` writer - Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt."]
16pub type MST_TXFIFO_UDF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
17#[doc = "Field `TRANS_COMPLETE` writer - Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt."]
18pub type TRANS_COMPLETE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
19#[doc = "Field `TIME_OUT` writer - Set this bit to clear the I2C_TIME_OUT_INT interrupt."]
20pub type TIME_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
21#[doc = "Field `TRANS_START` writer - Set this bit to clear the I2C_TRANS_START_INT interrupt."]
22pub type TRANS_START_W<'a, REG> = crate::BitWriter1C<'a, REG>;
23#[doc = "Field `NACK` writer - Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt."]
24pub type NACK_W<'a, REG> = crate::BitWriter1C<'a, REG>;
25#[doc = "Field `TXFIFO_OVF` writer - Set this bit to clear I2C_TXFIFO_OVF_INT interrupt."]
26pub type TXFIFO_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
27#[doc = "Field `RXFIFO_UDF` writer - Set this bit to clear I2C_RXFIFO_UDF_INT interrupt."]
28pub type RXFIFO_UDF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
29#[doc = "Field `SCL_ST_TO` writer - Set this bit to clear I2C_SCL_ST_TO_INT interrupt."]
30pub type SCL_ST_TO_W<'a, REG> = crate::BitWriter1C<'a, REG>;
31#[doc = "Field `SCL_MAIN_ST_TO` writer - Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt."]
32pub type SCL_MAIN_ST_TO_W<'a, REG> = crate::BitWriter1C<'a, REG>;
33#[doc = "Field `DET_START` writer - Set this bit to clear I2C_DET_START_INT interrupt."]
34pub type DET_START_W<'a, REG> = crate::BitWriter1C<'a, REG>;
35#[doc = "Field `SLAVE_STRETCH` writer - Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt."]
36pub type SLAVE_STRETCH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
37#[doc = "Field `GENERAL_CALL` writer - Set this bit to clear I2C_GENARAL_CALL_INT interrupt."]
38pub type GENERAL_CALL_W<'a, REG> = crate::BitWriter1C<'a, REG>;
39#[doc = "Field `SLAVE_ADDR_UNMATCH` writer - Set this bit to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt."]
40pub type SLAVE_ADDR_UNMATCH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
41#[cfg(feature = "impl-register-debug")]
42impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
43 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
44 write!(f, "(not readable)")
45 }
46}
47impl W {
48 #[doc = "Bit 0 - Set this bit to clear I2C_RXFIFO_WM_INT interrupt."]
49 #[inline(always)]
50 pub fn rxfifo_wm(&mut self) -> RXFIFO_WM_W<INT_CLR_SPEC> {
51 RXFIFO_WM_W::new(self, 0)
52 }
53 #[doc = "Bit 1 - Set this bit to clear I2C_TXFIFO_WM_INT interrupt."]
54 #[inline(always)]
55 pub fn txfifo_wm(&mut self) -> TXFIFO_WM_W<INT_CLR_SPEC> {
56 TXFIFO_WM_W::new(self, 1)
57 }
58 #[doc = "Bit 2 - Set this bit to clear I2C_RXFIFO_OVF_INT interrupt."]
59 #[inline(always)]
60 pub fn rxfifo_ovf(&mut self) -> RXFIFO_OVF_W<INT_CLR_SPEC> {
61 RXFIFO_OVF_W::new(self, 2)
62 }
63 #[doc = "Bit 3 - Set this bit to clear the I2C_END_DETECT_INT interrupt."]
64 #[inline(always)]
65 pub fn end_detect(&mut self) -> END_DETECT_W<INT_CLR_SPEC> {
66 END_DETECT_W::new(self, 3)
67 }
68 #[doc = "Bit 4 - Set this bit to clear the I2C_END_DETECT_INT interrupt."]
69 #[inline(always)]
70 pub fn byte_trans_done(&mut self) -> BYTE_TRANS_DONE_W<INT_CLR_SPEC> {
71 BYTE_TRANS_DONE_W::new(self, 4)
72 }
73 #[doc = "Bit 5 - Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt."]
74 #[inline(always)]
75 pub fn arbitration_lost(&mut self) -> ARBITRATION_LOST_W<INT_CLR_SPEC> {
76 ARBITRATION_LOST_W::new(self, 5)
77 }
78 #[doc = "Bit 6 - Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt."]
79 #[inline(always)]
80 pub fn mst_txfifo_udf(&mut self) -> MST_TXFIFO_UDF_W<INT_CLR_SPEC> {
81 MST_TXFIFO_UDF_W::new(self, 6)
82 }
83 #[doc = "Bit 7 - Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt."]
84 #[inline(always)]
85 pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<INT_CLR_SPEC> {
86 TRANS_COMPLETE_W::new(self, 7)
87 }
88 #[doc = "Bit 8 - Set this bit to clear the I2C_TIME_OUT_INT interrupt."]
89 #[inline(always)]
90 pub fn time_out(&mut self) -> TIME_OUT_W<INT_CLR_SPEC> {
91 TIME_OUT_W::new(self, 8)
92 }
93 #[doc = "Bit 9 - Set this bit to clear the I2C_TRANS_START_INT interrupt."]
94 #[inline(always)]
95 pub fn trans_start(&mut self) -> TRANS_START_W<INT_CLR_SPEC> {
96 TRANS_START_W::new(self, 9)
97 }
98 #[doc = "Bit 10 - Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt."]
99 #[inline(always)]
100 pub fn nack(&mut self) -> NACK_W<INT_CLR_SPEC> {
101 NACK_W::new(self, 10)
102 }
103 #[doc = "Bit 11 - Set this bit to clear I2C_TXFIFO_OVF_INT interrupt."]
104 #[inline(always)]
105 pub fn txfifo_ovf(&mut self) -> TXFIFO_OVF_W<INT_CLR_SPEC> {
106 TXFIFO_OVF_W::new(self, 11)
107 }
108 #[doc = "Bit 12 - Set this bit to clear I2C_RXFIFO_UDF_INT interrupt."]
109 #[inline(always)]
110 pub fn rxfifo_udf(&mut self) -> RXFIFO_UDF_W<INT_CLR_SPEC> {
111 RXFIFO_UDF_W::new(self, 12)
112 }
113 #[doc = "Bit 13 - Set this bit to clear I2C_SCL_ST_TO_INT interrupt."]
114 #[inline(always)]
115 pub fn scl_st_to(&mut self) -> SCL_ST_TO_W<INT_CLR_SPEC> {
116 SCL_ST_TO_W::new(self, 13)
117 }
118 #[doc = "Bit 14 - Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt."]
119 #[inline(always)]
120 pub fn scl_main_st_to(&mut self) -> SCL_MAIN_ST_TO_W<INT_CLR_SPEC> {
121 SCL_MAIN_ST_TO_W::new(self, 14)
122 }
123 #[doc = "Bit 15 - Set this bit to clear I2C_DET_START_INT interrupt."]
124 #[inline(always)]
125 pub fn det_start(&mut self) -> DET_START_W<INT_CLR_SPEC> {
126 DET_START_W::new(self, 15)
127 }
128 #[doc = "Bit 16 - Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt."]
129 #[inline(always)]
130 pub fn slave_stretch(&mut self) -> SLAVE_STRETCH_W<INT_CLR_SPEC> {
131 SLAVE_STRETCH_W::new(self, 16)
132 }
133 #[doc = "Bit 17 - Set this bit to clear I2C_GENARAL_CALL_INT interrupt."]
134 #[inline(always)]
135 pub fn general_call(&mut self) -> GENERAL_CALL_W<INT_CLR_SPEC> {
136 GENERAL_CALL_W::new(self, 17)
137 }
138 #[doc = "Bit 18 - Set this bit to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt."]
139 #[inline(always)]
140 pub fn slave_addr_unmatch(&mut self) -> SLAVE_ADDR_UNMATCH_W<INT_CLR_SPEC> {
141 SLAVE_ADDR_UNMATCH_W::new(self, 18)
142 }
143}
144#[doc = "Interrupt clear bits\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
145pub struct INT_CLR_SPEC;
146impl crate::RegisterSpec for INT_CLR_SPEC {
147 type Ux = u32;
148}
149#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
150impl crate::Writable for INT_CLR_SPEC {
151 type Safety = crate::Unsafe;
152 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
153 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0007_ffff;
154}
155#[doc = "`reset()` method sets INT_CLR to value 0"]
156impl crate::Resettable for INT_CLR_SPEC {
157 const RESET_VALUE: u32 = 0;
158}