esp32c6/extmem/
l2_cache_preload_size.rs

1#[doc = "Register `L2_CACHE_PRELOAD_SIZE` reader"]
2pub type R = crate::R<L2_CACHE_PRELOAD_SIZE_SPEC>;
3#[doc = "Field `L2_CACHE_PRELOAD_SIZE` reader - Those bits are used to configure the size of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG"]
4pub type L2_CACHE_PRELOAD_SIZE_R = crate::FieldReader<u16>;
5impl R {
6    #[doc = "Bits 0:15 - Those bits are used to configure the size of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG"]
7    #[inline(always)]
8    pub fn l2_cache_preload_size(&self) -> L2_CACHE_PRELOAD_SIZE_R {
9        L2_CACHE_PRELOAD_SIZE_R::new((self.bits & 0xffff) as u16)
10    }
11}
12#[cfg(feature = "impl-register-debug")]
13impl core::fmt::Debug for R {
14    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
15        f.debug_struct("L2_CACHE_PRELOAD_SIZE")
16            .field("l2_cache_preload_size", &self.l2_cache_preload_size())
17            .finish()
18    }
19}
20#[doc = "L2 Cache preload size configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`l2_cache_preload_size::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21pub struct L2_CACHE_PRELOAD_SIZE_SPEC;
22impl crate::RegisterSpec for L2_CACHE_PRELOAD_SIZE_SPEC {
23    type Ux = u32;
24}
25#[doc = "`read()` method returns [`l2_cache_preload_size::R`](R) reader structure"]
26impl crate::Readable for L2_CACHE_PRELOAD_SIZE_SPEC {}
27#[doc = "`reset()` method sets L2_CACHE_PRELOAD_SIZE to value 0"]
28impl crate::Resettable for L2_CACHE_PRELOAD_SIZE_SPEC {
29    const RESET_VALUE: u32 = 0;
30}
esp32c6/extmem/l2_cache_preload_size.rs

esp32c6/extmem/
l2_cache_preload_size.rs
