esp32c6/extmem/
l1_icache2_preload_ctrl.rs

1#[doc = "Register `L1_ICACHE2_PRELOAD_CTRL` reader"]
2pub type R = crate::R<L1_ICACHE2_PRELOAD_CTRL_SPEC>;
3#[doc = "Register `L1_ICACHE2_PRELOAD_CTRL` writer"]
4pub type W = crate::W<L1_ICACHE2_PRELOAD_CTRL_SPEC>;
5#[doc = "Field `L1_ICACHE2_PRELOAD_ENA` reader - The bit is used to enable preload operation on L1-ICache2. It will be cleared by hardware automatically after preload operation is done."]
6pub type L1_ICACHE2_PRELOAD_ENA_R = crate::BitReader;
7#[doc = "Field `L1_ICACHE2_PRELOAD_ENA` writer - The bit is used to enable preload operation on L1-ICache2. It will be cleared by hardware automatically after preload operation is done."]
8pub type L1_ICACHE2_PRELOAD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `L1_ICACHE2_PRELOAD_DONE` reader - The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished."]
10pub type L1_ICACHE2_PRELOAD_DONE_R = crate::BitReader;
11#[doc = "Field `L1_ICACHE2_PRELOAD_ORDER` reader - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending."]
12pub type L1_ICACHE2_PRELOAD_ORDER_R = crate::BitReader;
13#[doc = "Field `L1_ICACHE2_PRELOAD_RGID` reader - The bit is used to set the gid of l1 icache2 preload."]
14pub type L1_ICACHE2_PRELOAD_RGID_R = crate::FieldReader;
15impl R {
16    #[doc = "Bit 0 - The bit is used to enable preload operation on L1-ICache2. It will be cleared by hardware automatically after preload operation is done."]
17    #[inline(always)]
18    pub fn l1_icache2_preload_ena(&self) -> L1_ICACHE2_PRELOAD_ENA_R {
19        L1_ICACHE2_PRELOAD_ENA_R::new((self.bits & 1) != 0)
20    }
21    #[doc = "Bit 1 - The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished."]
22    #[inline(always)]
23    pub fn l1_icache2_preload_done(&self) -> L1_ICACHE2_PRELOAD_DONE_R {
24        L1_ICACHE2_PRELOAD_DONE_R::new(((self.bits >> 1) & 1) != 0)
25    }
26    #[doc = "Bit 2 - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending."]
27    #[inline(always)]
28    pub fn l1_icache2_preload_order(&self) -> L1_ICACHE2_PRELOAD_ORDER_R {
29        L1_ICACHE2_PRELOAD_ORDER_R::new(((self.bits >> 2) & 1) != 0)
30    }
31    #[doc = "Bits 3:6 - The bit is used to set the gid of l1 icache2 preload."]
32    #[inline(always)]
33    pub fn l1_icache2_preload_rgid(&self) -> L1_ICACHE2_PRELOAD_RGID_R {
34        L1_ICACHE2_PRELOAD_RGID_R::new(((self.bits >> 3) & 0x0f) as u8)
35    }
36}
37#[cfg(feature = "impl-register-debug")]
38impl core::fmt::Debug for R {
39    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
40        f.debug_struct("L1_ICACHE2_PRELOAD_CTRL")
41            .field("l1_icache2_preload_ena", &self.l1_icache2_preload_ena())
42            .field("l1_icache2_preload_done", &self.l1_icache2_preload_done())
43            .field("l1_icache2_preload_order", &self.l1_icache2_preload_order())
44            .field("l1_icache2_preload_rgid", &self.l1_icache2_preload_rgid())
45            .finish()
46    }
47}
48impl W {
49    #[doc = "Bit 0 - The bit is used to enable preload operation on L1-ICache2. It will be cleared by hardware automatically after preload operation is done."]
50    #[inline(always)]
51    pub fn l1_icache2_preload_ena(
52        &mut self,
53    ) -> L1_ICACHE2_PRELOAD_ENA_W<L1_ICACHE2_PRELOAD_CTRL_SPEC> {
54        L1_ICACHE2_PRELOAD_ENA_W::new(self, 0)
55    }
56}
57#[doc = "L1 instruction Cache 2 preload-operation control register\n\nYou can [`read`](crate::Reg::read) this register and get [`l1_icache2_preload_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`l1_icache2_preload_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
58pub struct L1_ICACHE2_PRELOAD_CTRL_SPEC;
59impl crate::RegisterSpec for L1_ICACHE2_PRELOAD_CTRL_SPEC {
60    type Ux = u32;
61}
62#[doc = "`read()` method returns [`l1_icache2_preload_ctrl::R`](R) reader structure"]
63impl crate::Readable for L1_ICACHE2_PRELOAD_CTRL_SPEC {}
64#[doc = "`write(|w| ..)` method takes [`l1_icache2_preload_ctrl::W`](W) writer structure"]
65impl crate::Writable for L1_ICACHE2_PRELOAD_CTRL_SPEC {
66    type Safety = crate::Unsafe;
67    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
68    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
69}
70#[doc = "`reset()` method sets L1_ICACHE2_PRELOAD_CTRL to value 0x02"]
71impl crate::Resettable for L1_ICACHE2_PRELOAD_CTRL_SPEC {
72    const RESET_VALUE: u32 = 0x02;
73}
esp32c6/extmem/l1_icache2_preload_ctrl.rs

esp32c6/extmem/
l1_icache2_preload_ctrl.rs
