esp32c6/extmem/
l1_icache0_preload_addr.rs

1#[doc = "Register `L1_ICACHE0_PRELOAD_ADDR` reader"]
2pub type R = crate::R<L1_ICACHE0_PRELOAD_ADDR_SPEC>;
3#[doc = "Field `L1_ICACHE0_PRELOAD_ADDR` reader - Those bits are used to configure the start virtual address of preload on L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG"]
4pub type L1_ICACHE0_PRELOAD_ADDR_R = crate::FieldReader<u32>;
5impl R {
6    #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of preload on L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG"]
7    #[inline(always)]
8    pub fn l1_icache0_preload_addr(&self) -> L1_ICACHE0_PRELOAD_ADDR_R {
9        L1_ICACHE0_PRELOAD_ADDR_R::new(self.bits)
10    }
11}
12#[cfg(feature = "impl-register-debug")]
13impl core::fmt::Debug for R {
14    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
15        f.debug_struct("L1_ICACHE0_PRELOAD_ADDR")
16            .field("l1_icache0_preload_addr", &self.l1_icache0_preload_addr())
17            .finish()
18    }
19}
20#[doc = "L1 instruction Cache 0 preload address configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`l1_icache0_preload_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21pub struct L1_ICACHE0_PRELOAD_ADDR_SPEC;
22impl crate::RegisterSpec for L1_ICACHE0_PRELOAD_ADDR_SPEC {
23    type Ux = u32;
24}
25#[doc = "`read()` method returns [`l1_icache0_preload_addr::R`](R) reader structure"]
26impl crate::Readable for L1_ICACHE0_PRELOAD_ADDR_SPEC {}
27#[doc = "`reset()` method sets L1_ICACHE0_PRELOAD_ADDR to value 0"]
28impl crate::Resettable for L1_ICACHE0_PRELOAD_ADDR_SPEC {
29    const RESET_VALUE: u32 = 0;
30}
esp32c6/extmem/l1_icache0_preload_addr.rs

esp32c6/extmem/
l1_icache0_preload_addr.rs
