esp32c6/extmem/
l1_cache_way_object.rs

1#[doc = "Register `L1_CACHE_WAY_OBJECT` reader"]
2pub type R = crate::R<L1_CACHE_WAY_OBJECT_SPEC>;
3#[doc = "Register `L1_CACHE_WAY_OBJECT` writer"]
4pub type W = crate::W<L1_CACHE_WAY_OBJECT_SPEC>;
5#[doc = "Field `L1_CACHE_WAY_OBJECT` reader - Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7."]
6pub type L1_CACHE_WAY_OBJECT_R = crate::FieldReader;
7#[doc = "Field `L1_CACHE_WAY_OBJECT` writer - Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7."]
8pub type L1_CACHE_WAY_OBJECT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
9impl R {
10    #[doc = "Bits 0:2 - Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7."]
11    #[inline(always)]
12    pub fn l1_cache_way_object(&self) -> L1_CACHE_WAY_OBJECT_R {
13        L1_CACHE_WAY_OBJECT_R::new((self.bits & 7) as u8)
14    }
15}
16#[cfg(feature = "impl-register-debug")]
17impl core::fmt::Debug for R {
18    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19        f.debug_struct("L1_CACHE_WAY_OBJECT")
20            .field("l1_cache_way_object", &self.l1_cache_way_object())
21            .finish()
22    }
23}
24impl W {
25    #[doc = "Bits 0:2 - Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7."]
26    #[inline(always)]
27    pub fn l1_cache_way_object(&mut self) -> L1_CACHE_WAY_OBJECT_W<L1_CACHE_WAY_OBJECT_SPEC> {
28        L1_CACHE_WAY_OBJECT_W::new(self, 0)
29    }
30}
31#[doc = "Cache Tag and Data memory way register\n\nYou can [`read`](crate::Reg::read) this register and get [`l1_cache_way_object::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`l1_cache_way_object::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
32pub struct L1_CACHE_WAY_OBJECT_SPEC;
33impl crate::RegisterSpec for L1_CACHE_WAY_OBJECT_SPEC {
34    type Ux = u32;
35}
36#[doc = "`read()` method returns [`l1_cache_way_object::R`](R) reader structure"]
37impl crate::Readable for L1_CACHE_WAY_OBJECT_SPEC {}
38#[doc = "`write(|w| ..)` method takes [`l1_cache_way_object::W`](W) writer structure"]
39impl crate::Writable for L1_CACHE_WAY_OBJECT_SPEC {
40    type Safety = crate::Unsafe;
41    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
42    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
43}
44#[doc = "`reset()` method sets L1_CACHE_WAY_OBJECT to value 0"]
45impl crate::Resettable for L1_CACHE_WAY_OBJECT_SPEC {
46    const RESET_VALUE: u32 = 0;
47}
esp32c6/extmem/l1_cache_way_object.rs

esp32c6/extmem/
l1_cache_way_object.rs
