esp32c6/dma/in_int_ch/
clr.rs

1#[doc = "Register `CLR` writer"]
2pub type W = crate::W<CLR_SPEC>;
3#[doc = "Field `IN_DONE` writer - Set this bit to clear the IN_DONE_CH_INT interrupt."]
4pub type IN_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `IN_SUC_EOF` writer - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."]
6pub type IN_SUC_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `IN_ERR_EOF` writer - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."]
8pub type IN_ERR_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `IN_DSCR_ERR` writer - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt."]
10pub type IN_DSCR_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
11#[doc = "Field `IN_DSCR_EMPTY` writer - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."]
12pub type IN_DSCR_EMPTY_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `INFIFO_OVF` writer - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."]
14pub type INFIFO_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
15#[doc = "Field `INFIFO_UDF` writer - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."]
16pub type INFIFO_UDF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
17#[cfg(feature = "impl-register-debug")]
18impl core::fmt::Debug for crate::generic::Reg<CLR_SPEC> {
19    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
20        write!(f, "(not readable)")
21    }
22}
23impl W {
24    #[doc = "Bit 0 - Set this bit to clear the IN_DONE_CH_INT interrupt."]
25    #[inline(always)]
26    pub fn in_done(&mut self) -> IN_DONE_W<CLR_SPEC> {
27        IN_DONE_W::new(self, 0)
28    }
29    #[doc = "Bit 1 - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."]
30    #[inline(always)]
31    pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<CLR_SPEC> {
32        IN_SUC_EOF_W::new(self, 1)
33    }
34    #[doc = "Bit 2 - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."]
35    #[inline(always)]
36    pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<CLR_SPEC> {
37        IN_ERR_EOF_W::new(self, 2)
38    }
39    #[doc = "Bit 3 - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt."]
40    #[inline(always)]
41    pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<CLR_SPEC> {
42        IN_DSCR_ERR_W::new(self, 3)
43    }
44    #[doc = "Bit 4 - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."]
45    #[inline(always)]
46    pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<CLR_SPEC> {
47        IN_DSCR_EMPTY_W::new(self, 4)
48    }
49    #[doc = "Bit 5 - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."]
50    #[inline(always)]
51    pub fn infifo_ovf(&mut self) -> INFIFO_OVF_W<CLR_SPEC> {
52        INFIFO_OVF_W::new(self, 5)
53    }
54    #[doc = "Bit 6 - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."]
55    #[inline(always)]
56    pub fn infifo_udf(&mut self) -> INFIFO_UDF_W<CLR_SPEC> {
57        INFIFO_UDF_W::new(self, 6)
58    }
59}
60#[doc = "Interrupt clear bits of channel 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
61pub struct CLR_SPEC;
62impl crate::RegisterSpec for CLR_SPEC {
63    type Ux = u32;
64}
65#[doc = "`write(|w| ..)` method takes [`clr::W`](W) writer structure"]
66impl crate::Writable for CLR_SPEC {
67    type Safety = crate::Unsafe;
68    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
69    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x7f;
70}
71#[doc = "`reset()` method sets CLR to value 0"]
72impl crate::Resettable for CLR_SPEC {
73    const RESET_VALUE: u32 = 0;
74}
esp32c6/dma/in_int_ch/clr.rs

esp32c6/dma/in_int_ch/
clr.rs
