1#[doc = "Register `USER` reader"]
2pub type R = crate::R<USER_SPEC>;
3#[doc = "Register `USER` writer"]
4pub type W = crate::W<USER_SPEC>;
5#[doc = "Field `CK_OUT_EDGE` reader - the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode."]
6pub type CK_OUT_EDGE_R = crate::BitReader;
7#[doc = "Field `CK_OUT_EDGE` writer - the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode."]
8pub type CK_OUT_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `FWRITE_DUAL` reader - In the write operations read-data phase apply 2 signals"]
10pub type FWRITE_DUAL_R = crate::BitReader;
11#[doc = "Field `FWRITE_DUAL` writer - In the write operations read-data phase apply 2 signals"]
12pub type FWRITE_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `FWRITE_QUAD` reader - In the write operations read-data phase apply 4 signals"]
14pub type FWRITE_QUAD_R = crate::BitReader;
15#[doc = "Field `FWRITE_QUAD` writer - In the write operations read-data phase apply 4 signals"]
16pub type FWRITE_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `FWRITE_DIO` reader - In the write operations address phase and read-data phase apply 2 signals."]
18pub type FWRITE_DIO_R = crate::BitReader;
19#[doc = "Field `FWRITE_DIO` writer - In the write operations address phase and read-data phase apply 2 signals."]
20pub type FWRITE_DIO_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `FWRITE_QIO` reader - In the write operations address phase and read-data phase apply 4 signals."]
22pub type FWRITE_QIO_R = crate::BitReader;
23#[doc = "Field `FWRITE_QIO` writer - In the write operations address phase and read-data phase apply 4 signals."]
24pub type FWRITE_QIO_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `USR_MISO_HIGHPART` reader - read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable."]
26pub type USR_MISO_HIGHPART_R = crate::BitReader;
27#[doc = "Field `USR_MOSI_HIGHPART` reader - write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable."]
28pub type USR_MOSI_HIGHPART_R = crate::BitReader;
29#[doc = "Field `USR_DUMMY_IDLE` reader - SPI clock is disable in dummy phase when the bit is enable."]
30pub type USR_DUMMY_IDLE_R = crate::BitReader;
31#[doc = "Field `USR_DUMMY_IDLE` writer - SPI clock is disable in dummy phase when the bit is enable."]
32pub type USR_DUMMY_IDLE_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `USR_MOSI` reader - This bit enable the write-data phase of an operation."]
34pub type USR_MOSI_R = crate::BitReader;
35#[doc = "Field `USR_MOSI` writer - This bit enable the write-data phase of an operation."]
36pub type USR_MOSI_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `USR_MISO` reader - This bit enable the read-data phase of an operation."]
38pub type USR_MISO_R = crate::BitReader;
39#[doc = "Field `USR_MISO` writer - This bit enable the read-data phase of an operation."]
40pub type USR_MISO_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `USR_DUMMY` reader - This bit enable the dummy phase of an operation."]
42pub type USR_DUMMY_R = crate::BitReader;
43#[doc = "Field `USR_DUMMY` writer - This bit enable the dummy phase of an operation."]
44pub type USR_DUMMY_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `USR_ADDR` reader - This bit enable the address phase of an operation."]
46pub type USR_ADDR_R = crate::BitReader;
47#[doc = "Field `USR_ADDR` writer - This bit enable the address phase of an operation."]
48pub type USR_ADDR_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `USR_COMMAND` reader - This bit enable the command phase of an operation."]
50pub type USR_COMMAND_R = crate::BitReader;
51#[doc = "Field `USR_COMMAND` writer - This bit enable the command phase of an operation."]
52pub type USR_COMMAND_W<'a, REG> = crate::BitWriter<'a, REG>;
53impl R {
54 #[doc = "Bit 9 - the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode."]
55 #[inline(always)]
56 pub fn ck_out_edge(&self) -> CK_OUT_EDGE_R {
57 CK_OUT_EDGE_R::new(((self.bits >> 9) & 1) != 0)
58 }
59 #[doc = "Bit 12 - In the write operations read-data phase apply 2 signals"]
60 #[inline(always)]
61 pub fn fwrite_dual(&self) -> FWRITE_DUAL_R {
62 FWRITE_DUAL_R::new(((self.bits >> 12) & 1) != 0)
63 }
64 #[doc = "Bit 13 - In the write operations read-data phase apply 4 signals"]
65 #[inline(always)]
66 pub fn fwrite_quad(&self) -> FWRITE_QUAD_R {
67 FWRITE_QUAD_R::new(((self.bits >> 13) & 1) != 0)
68 }
69 #[doc = "Bit 14 - In the write operations address phase and read-data phase apply 2 signals."]
70 #[inline(always)]
71 pub fn fwrite_dio(&self) -> FWRITE_DIO_R {
72 FWRITE_DIO_R::new(((self.bits >> 14) & 1) != 0)
73 }
74 #[doc = "Bit 15 - In the write operations address phase and read-data phase apply 4 signals."]
75 #[inline(always)]
76 pub fn fwrite_qio(&self) -> FWRITE_QIO_R {
77 FWRITE_QIO_R::new(((self.bits >> 15) & 1) != 0)
78 }
79 #[doc = "Bit 24 - read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable."]
80 #[inline(always)]
81 pub fn usr_miso_highpart(&self) -> USR_MISO_HIGHPART_R {
82 USR_MISO_HIGHPART_R::new(((self.bits >> 24) & 1) != 0)
83 }
84 #[doc = "Bit 25 - write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable."]
85 #[inline(always)]
86 pub fn usr_mosi_highpart(&self) -> USR_MOSI_HIGHPART_R {
87 USR_MOSI_HIGHPART_R::new(((self.bits >> 25) & 1) != 0)
88 }
89 #[doc = "Bit 26 - SPI clock is disable in dummy phase when the bit is enable."]
90 #[inline(always)]
91 pub fn usr_dummy_idle(&self) -> USR_DUMMY_IDLE_R {
92 USR_DUMMY_IDLE_R::new(((self.bits >> 26) & 1) != 0)
93 }
94 #[doc = "Bit 27 - This bit enable the write-data phase of an operation."]
95 #[inline(always)]
96 pub fn usr_mosi(&self) -> USR_MOSI_R {
97 USR_MOSI_R::new(((self.bits >> 27) & 1) != 0)
98 }
99 #[doc = "Bit 28 - This bit enable the read-data phase of an operation."]
100 #[inline(always)]
101 pub fn usr_miso(&self) -> USR_MISO_R {
102 USR_MISO_R::new(((self.bits >> 28) & 1) != 0)
103 }
104 #[doc = "Bit 29 - This bit enable the dummy phase of an operation."]
105 #[inline(always)]
106 pub fn usr_dummy(&self) -> USR_DUMMY_R {
107 USR_DUMMY_R::new(((self.bits >> 29) & 1) != 0)
108 }
109 #[doc = "Bit 30 - This bit enable the address phase of an operation."]
110 #[inline(always)]
111 pub fn usr_addr(&self) -> USR_ADDR_R {
112 USR_ADDR_R::new(((self.bits >> 30) & 1) != 0)
113 }
114 #[doc = "Bit 31 - This bit enable the command phase of an operation."]
115 #[inline(always)]
116 pub fn usr_command(&self) -> USR_COMMAND_R {
117 USR_COMMAND_R::new(((self.bits >> 31) & 1) != 0)
118 }
119}
120#[cfg(feature = "impl-register-debug")]
121impl core::fmt::Debug for R {
122 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
123 f.debug_struct("USER")
124 .field("ck_out_edge", &self.ck_out_edge())
125 .field("fwrite_dual", &self.fwrite_dual())
126 .field("fwrite_quad", &self.fwrite_quad())
127 .field("fwrite_dio", &self.fwrite_dio())
128 .field("fwrite_qio", &self.fwrite_qio())
129 .field("usr_miso_highpart", &self.usr_miso_highpart())
130 .field("usr_mosi_highpart", &self.usr_mosi_highpart())
131 .field("usr_dummy_idle", &self.usr_dummy_idle())
132 .field("usr_mosi", &self.usr_mosi())
133 .field("usr_miso", &self.usr_miso())
134 .field("usr_dummy", &self.usr_dummy())
135 .field("usr_addr", &self.usr_addr())
136 .field("usr_command", &self.usr_command())
137 .finish()
138 }
139}
140impl W {
141 #[doc = "Bit 9 - the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode."]
142 #[inline(always)]
143 pub fn ck_out_edge(&mut self) -> CK_OUT_EDGE_W<USER_SPEC> {
144 CK_OUT_EDGE_W::new(self, 9)
145 }
146 #[doc = "Bit 12 - In the write operations read-data phase apply 2 signals"]
147 #[inline(always)]
148 pub fn fwrite_dual(&mut self) -> FWRITE_DUAL_W<USER_SPEC> {
149 FWRITE_DUAL_W::new(self, 12)
150 }
151 #[doc = "Bit 13 - In the write operations read-data phase apply 4 signals"]
152 #[inline(always)]
153 pub fn fwrite_quad(&mut self) -> FWRITE_QUAD_W<USER_SPEC> {
154 FWRITE_QUAD_W::new(self, 13)
155 }
156 #[doc = "Bit 14 - In the write operations address phase and read-data phase apply 2 signals."]
157 #[inline(always)]
158 pub fn fwrite_dio(&mut self) -> FWRITE_DIO_W<USER_SPEC> {
159 FWRITE_DIO_W::new(self, 14)
160 }
161 #[doc = "Bit 15 - In the write operations address phase and read-data phase apply 4 signals."]
162 #[inline(always)]
163 pub fn fwrite_qio(&mut self) -> FWRITE_QIO_W<USER_SPEC> {
164 FWRITE_QIO_W::new(self, 15)
165 }
166 #[doc = "Bit 26 - SPI clock is disable in dummy phase when the bit is enable."]
167 #[inline(always)]
168 pub fn usr_dummy_idle(&mut self) -> USR_DUMMY_IDLE_W<USER_SPEC> {
169 USR_DUMMY_IDLE_W::new(self, 26)
170 }
171 #[doc = "Bit 27 - This bit enable the write-data phase of an operation."]
172 #[inline(always)]
173 pub fn usr_mosi(&mut self) -> USR_MOSI_W<USER_SPEC> {
174 USR_MOSI_W::new(self, 27)
175 }
176 #[doc = "Bit 28 - This bit enable the read-data phase of an operation."]
177 #[inline(always)]
178 pub fn usr_miso(&mut self) -> USR_MISO_W<USER_SPEC> {
179 USR_MISO_W::new(self, 28)
180 }
181 #[doc = "Bit 29 - This bit enable the dummy phase of an operation."]
182 #[inline(always)]
183 pub fn usr_dummy(&mut self) -> USR_DUMMY_W<USER_SPEC> {
184 USR_DUMMY_W::new(self, 29)
185 }
186 #[doc = "Bit 30 - This bit enable the address phase of an operation."]
187 #[inline(always)]
188 pub fn usr_addr(&mut self) -> USR_ADDR_W<USER_SPEC> {
189 USR_ADDR_W::new(self, 30)
190 }
191 #[doc = "Bit 31 - This bit enable the command phase of an operation."]
192 #[inline(always)]
193 pub fn usr_command(&mut self) -> USR_COMMAND_W<USER_SPEC> {
194 USR_COMMAND_W::new(self, 31)
195 }
196}
197#[doc = "SPI1 user register.\n\nYou can [`read`](crate::Reg::read) this register and get [`user::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`user::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
198pub struct USER_SPEC;
199impl crate::RegisterSpec for USER_SPEC {
200 type Ux = u32;
201}
202#[doc = "`read()` method returns [`user::R`](R) reader structure"]
203impl crate::Readable for USER_SPEC {}
204#[doc = "`write(|w| ..)` method takes [`user::W`](W) writer structure"]
205impl crate::Writable for USER_SPEC {
206 type Safety = crate::Unsafe;
207 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
208 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
209}
210#[doc = "`reset()` method sets USER to value 0x8000_0000"]
211impl crate::Resettable for USER_SPEC {
212 const RESET_VALUE: u32 = 0x8000_0000;
213}