esp32c6/spi0/
cmd.rs

1#[doc = "Register `CMD` reader"]
2pub type R = crate::R<CMD_SPEC>;
3#[doc = "Field `MST_ST` reader - The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state."]
4pub type MST_ST_R = crate::FieldReader;
5#[doc = "Field `SLV_ST` reader - The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state."]
6pub type SLV_ST_R = crate::FieldReader;
7#[doc = "Field `USR` reader - SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
8pub type USR_R = crate::BitReader;
9impl R {
10    #[doc = "Bits 0:3 - The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state."]
11    #[inline(always)]
12    pub fn mst_st(&self) -> MST_ST_R {
13        MST_ST_R::new((self.bits & 0x0f) as u8)
14    }
15    #[doc = "Bits 4:7 - The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state."]
16    #[inline(always)]
17    pub fn slv_st(&self) -> SLV_ST_R {
18        SLV_ST_R::new(((self.bits >> 4) & 0x0f) as u8)
19    }
20    #[doc = "Bit 18 - SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
21    #[inline(always)]
22    pub fn usr(&self) -> USR_R {
23        USR_R::new(((self.bits >> 18) & 1) != 0)
24    }
25}
26#[cfg(feature = "impl-register-debug")]
27impl core::fmt::Debug for R {
28    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
29        f.debug_struct("CMD")
30            .field("mst_st", &self.mst_st())
31            .field("slv_st", &self.slv_st())
32            .field("usr", &self.usr())
33            .finish()
34    }
35}
36#[doc = "SPI0 FSM status register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
37pub struct CMD_SPEC;
38impl crate::RegisterSpec for CMD_SPEC {
39    type Ux = u32;
40}
41#[doc = "`read()` method returns [`cmd::R`](R) reader structure"]
42impl crate::Readable for CMD_SPEC {}
43#[doc = "`reset()` method sets CMD to value 0"]
44impl crate::Resettable for CMD_SPEC {
45    const RESET_VALUE: u32 = 0;
46}
esp32c6/spi0/cmd.rs

esp32c6/spi0/
cmd.rs
